The search functionality is under construction.
The search functionality is under construction.

Author Search Result

[Author] Hao YE(3hit)

1-3hit
  • A Framework for Goodput Optimization in P2P Streaming over Wireless Ad-Hoc Networks

    Hao YE  Kaiping XUE  Peilin HONG  Hancheng LU  

     
    PAPER-Network

      Vol:
    E94-B No:9
      Page(s):
    2511-2520

    Since the Content Distribution Network (CDN) and IP multicast have heavy infrastructure requirements, their deployment is quite restricted. In contrast, peer-to-peer (P2P) streaming applications are independent on infrastructures and thus have been widely deployed. Emerging wireless ad-hoc networks are poised to enable a variety of streaming applications. However, many potential problems, that are trivial in wired networks, will emerge when deploying existing P2P streaming applications directly into wireless ad-hoc networks. In this paper, we propose a goodput optimization framework for P2P streaming over wireless ad-hoc networks. A two-level buffer architecture is proposed to reassign the naive streaming systems' data requests. The framework adopts a chunk size-varying transmission algorithm to obtain smooth playback experience and acceptable overhead and utilize limited bandwidth resources efficiently. The distinguishing features of our implementation are as follows: first, the framework works as a middleware and is independent on the streaming service properties; existing P2P streaming application can be deployed in wireless ad-hoc networks with minimum modifications and development cost; second, the proposed algorithm can reduce unnecessary communication overheads compared with traditional algorithms which gain high playback continuity with small chunk size; finally, our scheme can utilize low bandwidth transmission paths rather than discarding them, and thus improve overall performance of the wireless network. We also present a set of experiments to show the effectiveness of the proposed mechanism.

  • Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy

    Jinghao YE  Masao YANAGISAWA  Youhua SHI  

     
    PAPER

      Vol:
    E103-A No:9
      Page(s):
    1063-1070

    To solve the area and power problems in Finite Impulse Response (FIR) implementations, a faithfully truncated adder-based FIR design is presented in this paper for significant area and power savings while the predefined output accuracy can still be obtained. As a solution to the accuracy loss caused by truncated adders, a static error analysis on the utilization of truncated adders in FIRs was performed. According to the mathematical analysis, we show that, with a given accuracy constraint, the optimal truncated adder configuration for an area-power efficient FIR design can be effortlessly determined. Evaluation results on various FIR implementations by using the proposed faithfully truncated adder designs showed that up to 35.4% and 27.9% savings in area and power consumption can be achieved with less than 1 ulp accuracy loss for uniformly distributed random inputs. Moreover, as a case study for normally distributed signals, a fixed 6-tap FIR is implemented for electrocardiogram (ECG) signal filtering was implemented, in which even with the increased truncated bits up to 10, the mean absolute error (Ē) can be guaranteed to be less than 1 ulp while up to 29.7% and 25.3% savings in area and power can be obtained.

  • Power-Aware Allocation of Chain-Like Real-Time Tasks on DVS Processors

    Chun-Chao YEH  

     
    PAPER-Computation and Computational Models

      Vol:
    E89-D No:12
      Page(s):
    2907-2918

    Viable techniques such as dynamic voltage scaling (DVS) provide a new design technique to balance system performance and energy saving. In this paper, we extend previous works on task assignment problems for a set of linear-pipeline tasks over a set of processors. Different from previous works, we revisit the problems with two additional system factors: deadline and energy-consumption, which are key factors in real-time and power-aware computation. We propose an O(nm2) time complexity algorithm to determine optimal task-assignment and speed-setting schemes leading to minimal energy consumption, for a given set of m real-time tasks running on n identical processors (with or without DVS supports). The same result can be extended to a restricted form of heterogeneous processor model. Meanwhile, we show that on homogeneous processor model more efficient algorithms can be applied and result in time complexity of O(m2) when m ≤ n. For completeness, we also discuss cases without contiguity constraints. We show under such cases the problems become at least as hard as NP-hard.