In order to satisfy the very high traffic demand in crowded hotspot areas and realize adequate security in future fifth-generation networks, this paper studies physical-layer security in the downlink of a two-tier ultra dense heterogeneous network, where a ubiquitous array formed by ultra dense deployed small-cells surrounds a macrocell base station. In this paper, the locations of legitimate users and eavesdroppers are drawn from Poisson point processes. Then, the cumulative distribution functions of the receive signal-to-interference-plus-noise ratio for legitimate users and eavesdroppers are derived. Further, the average secrecy rate and secrecy coverage probability for each tier as well as for the whole network are investigated. Finally, we analyze the influences on secrecy performance caused by eavesdropper density, transmit power allocation ratio, antenna number allocation ratio, and association area radius.

When debugging bugs, programmers often prepare test cases to reproduce buggy behaviours. However, for concurrent programs, test cases alone are typically insufficient to reproduce buggy behaviours, due to the nondeterminism of multi-threaded executions. In literature, various approaches have been proposed to reproduce buggy behaviours for concurrency bugs deterministically, but to the best of our knowledge, they are still limited. In particular, we have recognized three debugging scenarios from programming practice, but existing approaches can handle only one of the scenarios. In this paper, we propose a novel approach, called SPDebugger, that provides finer-grained thread controlling over test cases, programs under test, and even third party library code, to reproduce the predesigned thread execution schedule. The evaluation shows that SPDebugger handles more debugging scenarios than the state-of-the-art tool, called IMUnit, with similar human effort.

The proliferation of diverse kinds of programming languages and platforms makes it a common need to have the same functionality implemented in different languages for different platforms, such as Java for Android applications and C# for Windows phone applications. Although versions of code written in different languages appear syntactically quite different from each other, they are intended to implement the same software and typically contain many code snippets that implement similar functionalities, which we call cross-language clones. When the version of code in one language evolves according to changing functionality requirements and/or bug fixes, its cross-language clones may also need be changed to maintain consistent implementations for the same functionality. Thus, it is needed to have automated ways to locate and track cross-language clones within the evolving software. In the literature, approaches for detecting cross-language clones are only for languages that share a common intermediate language (such as the .NET language family) because they are built on techniques for detecting single-language clones. To extend the capability of cross-language clone detection to more diverse kinds of languages, we propose a novel automated approach, CLCMiner, without the need of an intermediate language. It mines such clones from revision histories, based on our assumption that revisions to different versions of code implemented in different languages may naturally reflect how programmers change cross-language clones in practice, and that similarities among the revisions (referred to as clones in diffs or diff clones) may indicate actual similar code. We have implemented a prototype and applied it to ten open source projects implementations in both Java and C#. The reported clones that occur in revision histories are of high precisions (89% on average) and recalls (95% on average). Compared with token-based code clone detection tools that can treat code as plain texts, our tool can detect significantly more cross-language clones. All the evaluation results demonstrate the feasibility of revision-history based techniques for detecting cross-language clones without intermediates and point to promising future work.

In order to further optimize the power consumption of Pseudo-CMOS inverter, this paper proposes a Re-Pull-Down transistor scheme. Two additional transistors are used to build another pull-down network. With this design, the quiescent current of the inverter can be reduced while the ratioless nature is preserved. Based on the reduced input gate area, two output transistors are set wider to compensate for the pull-up speed. The simulation result shows that, compared with Pseudo-CMOS inverter, the maximum quiescent current of the Re-Pull-Down transistor scheme inverter is reduced by 37.6% in the static analysis. Besides, the average power consumption is reduced by 30.8% in the 5-stage ring oscillator test.