Ising machines have attracted attention as they are expected to solve combinatorial optimization problems at high speed with Ising models corresponding to those problems. An induced subgraph isomorphism problem is one of the decision problems, which determines whether a specific graph structure is included in a whole graph or not. The problem can be represented by equality constraints in the words of combinatorial optimization problem. By using the penalty functions corresponding to the equality constraints, we can utilize an Ising machine to the induced subgraph isomorphism problem. The induced subgraph isomorphism problem can be seen in many practical problems, for example, finding out a particular malicious circuit in a device or particular network structure of chemical bonds in a compound. However, due to the limitation of the number of spin variables in the current Ising machines, reducing the number of spin variables is a major concern. Here, we propose an efficient Ising model mapping method to solve the induced subgraph isomorphism problem by Ising machines. Our proposed method theoretically solves the induced subgraph isomorphism problem. Furthermore, the number of spin variables in the Ising model generated by our proposed method is theoretically smaller than that of the conventional method. Experimental results demonstrate that our proposed method can successfully solve the induced subgraph isomorphism problem by using the Ising-model based simulated annealing and a real Ising machine.

The effects of rapid thermal annealing (RTA) on bias-stress-induced base leakage were investigated in InGaP/GaAs collector-up heterojunction bipolar transistors (C-up HBTs) fabricated with boron ion implantation. C-up HBTs annealed at 700 for 1 s had negligible leakage, while non-annealed C-up HBTs had leakage (with an activation energy, Ea, of 0.17 eV) that exponentially increased with bias time. Because this Ea is almost the same as that of the hole traps (0.25 eV) observed in the InGaP emitters of non-annealed C-up HBTs, we attribute the leakage to hole tunneling from bases to emitters. By reducing the initial trap density using RTA, we stabilized current gain even after 1,030 h of testing at a junction temperature of 210 and a collector current density of 40 kA/cm2.