A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.

A Real-time Capacitor Compensation (RCC) scheme is proposed for low power and continuous communication in the wearable inductive coupling transceiver. Since inductance values of wearable inductor vary dynamically with deterioration of its communication characteristics, the inductance value is monitored and its resonance frequency is adjusted by additive parallel/serial capacitors in real time. RLC Bridge for detection of the inductance variations and the Dual-edge Sampling Comparator for recognition of the variance direction are proposed. It is implemented in a 0.18 µm CMOS technology, and it occupies a 12.7 mm2 chip area. The proposed transceiver consumes only 426.6 µW at 4 Mbps data rate. The compensation time takes 4.78 µs, including 3 µs of detection and 1.78 µs for compensation process in worst case.

In this paper, two low power hardware structures essential for MPEG-4 video codec are proposed for portable applications. First, an adaptive bit resolution control (ABRC) scheme is proposed for a processing element (PE) in a systolic-array type motion estimator (ME). By appropriately modifying the datapath of PE to exploit the correlations in pixel values, its structure is optimized in terms of both hardware cost and low power consumption. As a result, power is saved up to 29% compared with a conventional PE while the computation accuracy is preserved and the overhead is kept negligible. Second, a low power motion compensation (MC) accelerator is proposed. By embedding DRAM whose structure is optimized for low power consumption, the power consumption for external data I/Os is dramatically reduced. In addition, distributed nine-tiled block mapping (DNTBM) with partial activation scheme in the frame buffer reduces the power for accessing frame buffer up to 31% compared to a conventional 1-bank tiled mapping. With the proposed MC accelerator, MPEG-4 SP@L1 decoding system is fabricated using 0.18 µm embedded memory logic (EML) technology.

Embedded-DRAM (eDRAM) power-energy estimation model is proposed for system-on-a-chip (SOC) applications. The main feature is the signal swing based analytic (SSBA) model, which improves the accuracy of the conventional SRAM power-energy models. The power-energy estimation using SSBA model shows 95% accuracy compared with the transistor level power simulation for three fabricated eDRAMs. The SSBA model combined with the high-level simulator provides fast and accurate system level power-energy estimation of eDRAM.