A Low Voltage High Speed Self-Timed CMOS Logic for the Multi-Gigabit Synchronous DRAM Application
Summary :
A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.8 pp.1126-1128
- Publication Date
- 1997/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- Integrated Electronics
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Hoi-Jun YOO, "A Low Voltage High Speed Self-Timed CMOS Logic for the Multi-Gigabit Synchronous DRAM Application" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 8, pp. 1126-1128, August 1997, doi: .
Abstract: A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_8_1126/_p
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@ARTICLE{e80-c_8_1126,
author={Hoi-Jun YOO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low Voltage High Speed Self-Timed CMOS Logic for the Multi-Gigabit Synchronous DRAM Application},
year={1997},
volume={E80-C},
number={8},
pages={1126-1128},
abstract={A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - A Low Voltage High Speed Self-Timed CMOS Logic for the Multi-Gigabit Synchronous DRAM Application
T2 - IEICE TRANSACTIONS on Electronics
SP - 1126
EP - 1128
AU - Hoi-Jun YOO
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1997
AB - A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the self-timed circuit resets its own voltage to its standby state after 4 inverter delays. This pulsed nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme.
ER -
English
