We present an efficient heuristic algorithm to reduce glitch power dissipation in CMOS digital circuits. In this paper, gate sizing is classified into three types and the buffer insertion is classified into two types. The proposed algorithm combines three types of gate sizing and two types of buffer insertion into a single optimization process to maximize the glitch reduction. The efficiency of our algorithm has been verified on LGSynth91 benchmark circuits with a 0.5 µm standard cell library. Experimental results show an average of 69.98% glitch reduction and 28.69% power reduction that are much better than those of gate sizing and buffer insertion performed independently.

Signal integrity problem arises as one of the main issues in digital circuits manufactured by today's deep submicron technology. The coupling capacitance of neighboring lines may cause delays of circuit and it may affect the functionality of circuit. These effects are usually referred to as crosstalk. Since it requires additional design cost to fix crosstalk noise, the false aggressor nodes that cannot affect on victim node have to be eliminated. In this paper, we propose efficient heuristic algorithm that considers functional correlation for false aggressor pruning in crosstalk noise analysis. The false aggressors are detected by a path sensitization algorithm and logic implication. The efficiency of our algorithm has been verified on Benchmark circuits with a 0.18 µm standard cell library. Experimental results show an average of 5.4% false aggressor detection and an average improvement of 14.6% in the accuracy of timing analysis.

This paper presents methods of combining buffer insertion and transistor sizing into a single post-layout optimization. The proposed method considers the tradeoff between upsizing transistors and inserting buffers then chooses the solution with the lowest possible power and area cost. The proposed method is efficient and tunable in that optimality can be traded for compute time.