A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing
Summary :
This paper presents methods of combining buffer insertion and transistor sizing into a single post-layout optimization. The proposed method considers the tradeoff between upsizing transistors and inserting buffers then chooses the solution with the lowest possible power and area cost. The proposed method is efficient and tunable in that optimality can be traded for compute time.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.10 pp.2553-2560
- Publication Date
- 2001/10/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- VLSI Design Technology and CAD
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Sungkun LEE, Juho KIM, "A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 10, pp. 2553-2560, October 2001, doi: .
Abstract: This paper presents methods of combining buffer insertion and transistor sizing into a single post-layout optimization. The proposed method considers the tradeoff between upsizing transistors and inserting buffers then chooses the solution with the lowest possible power and area cost. The proposed method is efficient and tunable in that optimality can be traded for compute time.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_10_2553/_p
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@ARTICLE{e84-a_10_2553,
author={Sungkun LEE, Juho KIM, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing},
year={2001},
volume={E84-A},
number={10},
pages={2553-2560},
abstract={This paper presents methods of combining buffer insertion and transistor sizing into a single post-layout optimization. The proposed method considers the tradeoff between upsizing transistors and inserting buffers then chooses the solution with the lowest possible power and area cost. The proposed method is efficient and tunable in that optimality can be traded for compute time.},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2553
EP - 2560
AU - Sungkun LEE
AU - Juho KIM
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 10
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - October 2001
AB - This paper presents methods of combining buffer insertion and transistor sizing into a single post-layout optimization. The proposed method considers the tradeoff between upsizing transistors and inserting buffers then chooses the solution with the lowest possible power and area cost. The proposed method is efficient and tunable in that optimality can be traded for compute time.
ER -
English
