We have developed and fabricated an LSI called the FMPP-VQ64. The LSI is a memory-based shared-bus SIMD parallel processor containing 64 PEs, intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search (NNS) during vector quantization. The computation time does not depend on the number of code vectors. The FMPP-VQ64 performs 53,000 NNSs per second, while its power dissipation is 20 mW. It can be applied to the mobile telecommunication system.

The power consumption of optical network units (ONUs) is a major issue in optical access networks. The downstream buffer is one of the largest power consumers among the functional blocks of an ONU. A cyclic sleep scheme for reducing power has been reported, which periodically powers off not only the downstream buffer but also other components, such as optical transceivers, when the idle period is long. However, when the idle period is short, it cannot power off those components even if the input data rate is low. Therefore, as continuous traffic, such as video, increases, the power-reduction effect decreases. To resolve this issue, we propose another sleep scheme in which the downstream buffer can be partially powered off by cooperative operation with an optical line terminal. Simulation and experimental results indicate that the proposed scheme reduces ONU power consumption without causing frame loss even while the ONU continuously receives traffic and the idle period is short.

This paper describes ILS (Inter-frame Link Signaling) that provides SDH/SONET (Synchronous Digital Hierarchy/Synchronous Optical NETwork) compatible OAM&P (Operations, Administration, Maintenance, and Provisioning) functions for 10 GbE (10-Gbit/s Ethernet) physical layer links. ILS transports OAM&P overhead bytes by replacing Idles in interframe gaps and organizes virtual frames to emulate SDH/SONET overhead transport. The ILS coding scheme has three features: 10 GbE PHY transparency, error detection ability, and disparity neutral characteristics. A 10 GbE LAN-PHY media converter, one-chip PHY LSI, and a XENPAK transceiver embedded with ILS have been developed in order to facilitate ILS implementation in optical network systems or Ethernet equipment. We confirmed ILS's feasibility through an experiment using the media converters and XENPAKs. The ILS can achieve highly reliable and cost-effective 10 GbE transport over optical networks.

We propose a real-time low-rate video compression algorithm using fixed-rate multi-stage hierarchical vector quantization. Vector quantization is suitable for mobile computing, since it demands small computation on decoding. The proposed algorithm enables transmission of 10 QCIF frames per second over a low-rate 29.2 kbps mobile channel. A frame is hierarchically divided by sub-blocks. A frame of images is compressed in a fixed rate at any video activity. For active frames, large sub-blocks for low resolution are mainly transmitted. For inactive frames, smaller sub-blocks for high resolution can be transmitted successively after a motion-compensated frame. We develop a compression system which consists of a host computer and a memory-based processor for the nearest neighbor search on VQ. Our algorithm guarantees real-time decoding on a poor CPU.