IEICE TRANSACTIONS on Electronics
An LSI for Low Bit-Rate Image Compression Using Vector Quantization
Summary :
We have developed and fabricated an LSI called the FMPP-VQ64. The LSI is a memory-based shared-bus SIMD parallel processor containing 64 PEs, intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search (NNS) during vector quantization. The computation time does not depend on the number of code vectors. The FMPP-VQ64 performs 53,000 NNSs per second, while its power dissipation is 20 mW. It can be applied to the mobile telecommunication system.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E81-C No.5 pp.718-724
- Publication Date
- 1998/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
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Kazutoshi KOBAYASHI, Noritsugu NAKAMURA, Kazuhiko TERADA, Hidetoshi ONODERA, Keikichi TAMARU, "An LSI for Low Bit-Rate Image Compression Using Vector Quantization" in IEICE TRANSACTIONS on Electronics,
vol. E81-C, no. 5, pp. 718-724, May 1998, doi: .
Abstract: We have developed and fabricated an LSI called the FMPP-VQ64. The LSI is a memory-based shared-bus SIMD parallel processor containing 64 PEs, intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search (NNS) during vector quantization. The computation time does not depend on the number of code vectors. The FMPP-VQ64 performs 53,000 NNSs per second, while its power dissipation is 20 mW. It can be applied to the mobile telecommunication system.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e81-c_5_718/_p
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@ARTICLE{e81-c_5_718,
author={Kazutoshi KOBAYASHI, Noritsugu NAKAMURA, Kazuhiko TERADA, Hidetoshi ONODERA, Keikichi TAMARU, },
journal={IEICE TRANSACTIONS on Electronics},
title={An LSI for Low Bit-Rate Image Compression Using Vector Quantization},
year={1998},
volume={E81-C},
number={5},
pages={718-724},
abstract={We have developed and fabricated an LSI called the FMPP-VQ64. The LSI is a memory-based shared-bus SIMD parallel processor containing 64 PEs, intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search (NNS) during vector quantization. The computation time does not depend on the number of code vectors. The FMPP-VQ64 performs 53,000 NNSs per second, while its power dissipation is 20 mW. It can be applied to the mobile telecommunication system.},
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - An LSI for Low Bit-Rate Image Compression Using Vector Quantization
T2 - IEICE TRANSACTIONS on Electronics
SP - 718
EP - 724
AU - Kazutoshi KOBAYASHI
AU - Noritsugu NAKAMURA
AU - Kazuhiko TERADA
AU - Hidetoshi ONODERA
AU - Keikichi TAMARU
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1998
AB - We have developed and fabricated an LSI called the FMPP-VQ64. The LSI is a memory-based shared-bus SIMD parallel processor containing 64 PEs, intended for low bit-rate image compression using vector quantization. It accelerates the nearest neighbor search (NNS) during vector quantization. The computation time does not depend on the number of code vectors. The FMPP-VQ64 performs 53,000 NNSs per second, while its power dissipation is 20 mW. It can be applied to the mobile telecommunication system.
ER -
English
