A small data-line-swing read/write scheme is described for half-Vcc plate nonvolatile DRAMs with ferroelectric capacitors designed to achieve high reliability for read/write operations. In this scheme, the normal read/write operation holds the data as a charge with a small data-line-swing, and the store operation provides sufficient polarization with a full data-line-swing. This scheme enables high read/write endurance, because the small data-line-swing reduces the fatigue of the ferroelectric capacitor. Two circuit technologies are used in this scheme to increase the operating margin. The first is a plate voltage control technique that solves the polarization retention problem of half-Vcc plate nonvolatile DRAM technologies. The second is a doubled data-line-capacitance recall technique that connects two data lines to a cell and enlarges the readout signal compared to normal operation, when only one data line is connected to a cell. These techniques and circuits improve the write-cycle endurance by almost three orders of magnitude, while reducing the array power consumption during read/write operations to one-third that of conventional nonvolatile DRAMs.

The process mapping of the ALD process of HfO2 using HfCl4 and H2O is reported. A thickness uniformity better than 3% was achieved over a 300 mm-wafer at a deposition rate of 0.52 Å/cycle. Usually, H2O purge period is set less than 10 sec to obtain reasonable throughput; however, the amounts of residual impurities (Cl, H) found to be in the order of sub%, and these impurities are piled up near the HfO2/Si interface. In order to reduce the piled up impurities, we proposed a 2-step deposition in which purge period for initial 10-20 cycles was set to be 90 sec and that for remaining cycles was usual value of 7.5 sec. The leakage current is reduced to 1/10 by using this 2-step deposition.

We propose new test device structures, Gate-Last-formed structures, which are suitable for fundamental study of high-k gate insulator or metal gate electrode MISFETs. The gate insulator and electrode stack is formed after local interconnect pads connected with source and drain. The gate stack is build in trench formed by dry and wet etching and is non-self-aligned to the source and drain. The wet etching restricts damage formation on the exposed Si surface underneath the trench. Electrical characteristics are measurable just after exposure of surface of the local interconnect pads without conventional Al wiring. This structure can provide methods both for fundamental evaluation and for material selection of new gate stack materials by investigation of MISFET characteristics. This is achieved with short TAT and avoiding contamination penalty to a fab.