IEICE TRANSACTIONS on Electronics
Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs
Summary :
We propose new test device structures, Gate-Last-formed structures, which are suitable for fundamental study of high-k gate insulator or metal gate electrode MISFETs. The gate insulator and electrode stack is formed after local interconnect pads connected with source and drain. The gate stack is build in trench formed by dry and wet etching and is non-self-aligned to the source and drain. The wet etching restricts damage formation on the exposed Si surface underneath the trench. Electrical characteristics are measurable just after exposure of surface of the local interconnect pads without conventional Al wiring. This structure can provide methods both for fundamental evaluation and for material selection of new gate stack materials by investigation of MISFET characteristics. This is achieved with short TAT and avoiding contamination penalty to a fab.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.5 pp.804-810
- Publication Date
- 2005/05/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.5.804
- Type of Manuscript
- Special Section PAPER (Special Section on Microelectronic Test Structures)
- Category
Authors
Takeo MATSUKI
Kazuyoshi TORII
Takeshi MAEDA
Yasushi AKASAKA
Kiyoshi HAYASHI
Naoki KASAI
Tsunetoshi ARIKADO
Keyword
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Takeo MATSUKI, Kazuyoshi TORII, Takeshi MAEDA, Yasushi AKASAKA, Kiyoshi HAYASHI, Naoki KASAI, Tsunetoshi ARIKADO, "Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 5, pp. 804-810, May 2005, doi: 10.1093/ietele/e88-c.5.804.
Abstract: We propose new test device structures, Gate-Last-formed structures, which are suitable for fundamental study of high-k gate insulator or metal gate electrode MISFETs. The gate insulator and electrode stack is formed after local interconnect pads connected with source and drain. The gate stack is build in trench formed by dry and wet etching and is non-self-aligned to the source and drain. The wet etching restricts damage formation on the exposed Si surface underneath the trench. Electrical characteristics are measurable just after exposure of surface of the local interconnect pads without conventional Al wiring. This structure can provide methods both for fundamental evaluation and for material selection of new gate stack materials by investigation of MISFET characteristics. This is achieved with short TAT and avoiding contamination penalty to a fab.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.5.804/_p
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@ARTICLE{e88-c_5_804,
author={Takeo MATSUKI, Kazuyoshi TORII, Takeshi MAEDA, Yasushi AKASAKA, Kiyoshi HAYASHI, Naoki KASAI, Tsunetoshi ARIKADO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs},
year={2005},
volume={E88-C},
number={5},
pages={804-810},
abstract={We propose new test device structures, Gate-Last-formed structures, which are suitable for fundamental study of high-k gate insulator or metal gate electrode MISFETs. The gate insulator and electrode stack is formed after local interconnect pads connected with source and drain. The gate stack is build in trench formed by dry and wet etching and is non-self-aligned to the source and drain. The wet etching restricts damage formation on the exposed Si surface underneath the trench. Electrical characteristics are measurable just after exposure of surface of the local interconnect pads without conventional Al wiring. This structure can provide methods both for fundamental evaluation and for material selection of new gate stack materials by investigation of MISFET characteristics. This is achieved with short TAT and avoiding contamination penalty to a fab.},
keywords={},
doi={10.1093/ietele/e88-c.5.804},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - Gate-Last MISFET Structures and Process for Characterization of High-k and Metal Gate MISFETs
T2 - IEICE TRANSACTIONS on Electronics
SP - 804
EP - 810
AU - Takeo MATSUKI
AU - Kazuyoshi TORII
AU - Takeshi MAEDA
AU - Yasushi AKASAKA
AU - Kiyoshi HAYASHI
AU - Naoki KASAI
AU - Tsunetoshi ARIKADO
PY - 2005
DO - 10.1093/ietele/e88-c.5.804
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2005
AB - We propose new test device structures, Gate-Last-formed structures, which are suitable for fundamental study of high-k gate insulator or metal gate electrode MISFETs. The gate insulator and electrode stack is formed after local interconnect pads connected with source and drain. The gate stack is build in trench formed by dry and wet etching and is non-self-aligned to the source and drain. The wet etching restricts damage formation on the exposed Si surface underneath the trench. Electrical characteristics are measurable just after exposure of surface of the local interconnect pads without conventional Al wiring. This structure can provide methods both for fundamental evaluation and for material selection of new gate stack materials by investigation of MISFET characteristics. This is achieved with short TAT and avoiding contamination penalty to a fab.
ER -
English
