A flexible noise de-embedding method for on-wafer microwave measurements of silicon MOSFETs is presented in this study. We use the open, short, and thru dummy structures to subtract the parasitic effects from the probe pads and interconnects of a fixtured MOS transistor. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate, drain, and source terminals of the MOSFET. The parasitics of the dangling leg in the source terminal are also modeled and taken into account in the noise de-embedding procedure. The MOS transistors and de-embedding dummy structures were fabricated in a standard CMOS process and characterized up to 20 GHz. Compared with the conventional de-embedding methods, the proposed technique is accurate and area-efficient.

In this paper, we propose an accurate and scalable S-parameter de-embedding method for RF/microwave on-wafer characterization of silicon MOSFETs. Based on cascade configurations, this method utilizes planar open, short, and thru standards to estimate the effects of surrounding parasitic networks on a MOS transistor. The bulk-shielded open and short standards are used to simulate and de-embed the probe-pad parasitics. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate and drain terminals of the MOSFET. To further eliminate the parasitics of dangling leg in source terminal of the MOSFET, we also introduce the microwave and multi-port network analysis to accomplish the two-port-to-three-port transformation for S-parameters. The MOSFET and its corresponding de-embedding standards were fabricated in a standard CMOS process and characterized up to 40 GHz. The scalability of the open, short, and thru standards is demonstrated and the performance of the proposed de-embedding procedure is validated by comparison with several de-embedding techniques.

This paper considers uplink interleave division multiple access (IDMA), of which crucial requirement is the proper operability at a very low signal-to-interference-plus-noise power ratio (SINR) range. The primary objectives of this paper are threefold: (1) to demonstrate the achievability of near-capacity performance of bit interleaved coded modulation with iterative detection (BICM-ID) using very low rate single parity check and irregular repetition (SPC-IrR) codes at a very low SINR range, and hence the technique is effective in achieving excellent performance when it is applied for IDMA, (2) to propose a very simple multiuser detection (MUD) technique for the SPC-IrR BICM-ID IDMA which does not incur heavy per-iteration computational burden, and (3) to analyze the impacts of power allocation on the convergence property of MUD as well as on the rate region, by using the extrinsic information transfer (EXIT) chart. The SPC-IrR code parameters are optimized by using the EXIT-constrained binary switching algorithm (EBSA) at a very low SINR range. Simulation results show that the proposed technique can achieve excellent near-capacity performance with the bit error rate (BER) curves exhibiting very sharp threshold, which significantly influences the convergence property of MUD. Furthermore, this paper presents results of the rate region analysis of multiple access channel (MAC) in the cases of equal and unequal power allocation, as well as of a counterpart technique. The results of the MAC rate region analysis show that our proposed technique outperforms the counterpart technique.

In this paper, a novel and simple one-port de-embedding technique has been applied to through-silicon-via (TSV) characterization and modeling. This method utilized pad, via, and line structures to extract the equivalent circuit model of TSV. The main advantage of this de-embedding method is that it can reduce the chip area to fabricate test element groups (TEGs) for measurements while keeping S-parameter measurement accuracies. We also analyzed the electrical characteristics of substrate coupling and TSV equivalent impedance. Our results shows good agreements between measurement data and the equivalent circuit model up to 20GHz.

In this paper, an accurate experimental noise model to improve the EEHEMT nonlinear model using the Verilog-A language in Agilent ADS is presented for the first time. The present EEHEMT model adopts channel noise to model the noise behavior of pseudomorphic high electron mobility transistor (pHEMT). To enhance the accuracy of the EEHEMT noise model, we add two extra noise sources: gate shot noise and induced gate noise current. Here we demonstrate the power spectral density of the channel noise Sid and gate noise Sig versus gate-source voltage for 0.25 µm pHEMT devices. Additionally, the related noise source parameters, i.e., P, R, and C are presented. Finally, we compare four noise parameters between the simulation and model, and the agreement between the measurement and simulation results shows that this proposed approach is dependable and accurate.