This letter proposes a concurrent fault detection scheme for a butterfly unit in an FFT processor. A fault in a butterfly unit is detected by recomuting. Input data to the butterfly unit is coded by a bit rotation and used for recomputing. The recomputed outputs are decoded and compared with the output for the first computation. The hardware overhead for the scheme is O(N) and the time overhead is O(log (N)) where N is the number of input data.

This paper proposes a reconfigurable parallel processor based on a two-dimensional linear celular automaton model. The processor based on the model can be reconfigured quickly by utilizing the characteristics of the automaton used for its model. Moreover, the processor has short data path length between processing elements compared with the length of the processor based on one-dimensional linear cellular automaton model which has been already discussed. The processing elements of the processor based on the two-dimensional linear cellular automaton model are regarded as cells and the operational states of the processor are treated as the states of the automaton. When faults are detected, the processor can be reconfigured by changing its state under the state transition function of the processor determined by the weighting function of the automaton model. The processor can be reconfigured within a clock period required for making a state transition. This processor is extremely effective for real-time data processing systems required high reliability.

This paper presents a new language for writing specifications for digital systems. In the language (Buffer) to be described much attention has been given to its constructs for making the specifications understandable, precise enough, unambiguous, and easy to check for completeness and consistency.