Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practicality. This paper proposes a methodology and test patterns for exhaustively and systematically validating layout-aware compact models for general layout patterns for the first time. The methodology and test patterns are concretely shown through validation of a shallow trench isolation (STI) stress compact model proposed in [1]. First, the model parameters for a 55-nm CMOS technology are extracted, and then the model is verified and established to be accurate for the basic patterns used for parameter extraction. Next, fundamental ideas of model operation for general layout patterns are verified using various verification patterns. These tests revealed that the model is relatively weak in some cases not included in the basic patterns. Finally, the errors for these cases are eliminated by enhancing the algorithm. Consequently, the model is confirmed to have high generality. This methodology will be effective for validating other layout-aware compact models for general layout patterns.