Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practicality. This paper proposes a methodology and test patterns for exhaustively and systematically validating layout-aware compact models for general layout patterns for the first time. The methodology and test patterns are concretely shown through validation of a shallow trench isolation (STI) stress compact model proposed in [1]. First, the model parameters for a 55-nm CMOS technology are extracted, and then the model is verified and established to be accurate for the basic patterns used for parameter extraction. Next, fundamental ideas of model operation for general layout patterns are verified using various verification patterns. These tests revealed that the model is relatively weak in some cases not included in the basic patterns. Finally, the errors for these cases are eliminated by enhancing the algorithm. Consequently, the model is confirmed to have high generality. This methodology will be effective for validating other layout-aware compact models for general layout patterns.
Kenta YAMADA
Toshiyuki SYO
Hisao YOSHIMURA
Masaru ITO
Tatsuya KUNIKIYO
Toshiki KANAMOTO
Shigetaka KUMASHIRO
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Kenta YAMADA, Toshiyuki SYO, Hisao YOSHIMURA, Masaru ITO, Tatsuya KUNIKIYO, Toshiki KANAMOTO, Shigetaka KUMASHIRO, "Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 8, pp. 1349-1358, August 2010, doi: 10.1587/transele.E93.C.1349.
Abstract: Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practicality. This paper proposes a methodology and test patterns for exhaustively and systematically validating layout-aware compact models for general layout patterns for the first time. The methodology and test patterns are concretely shown through validation of a shallow trench isolation (STI) stress compact model proposed in [1]. First, the model parameters for a 55-nm CMOS technology are extracted, and then the model is verified and established to be accurate for the basic patterns used for parameter extraction. Next, fundamental ideas of model operation for general layout patterns are verified using various verification patterns. These tests revealed that the model is relatively weak in some cases not included in the basic patterns. Finally, the errors for these cases are eliminated by enhancing the algorithm. Consequently, the model is confirmed to have high generality. This methodology will be effective for validating other layout-aware compact models for general layout patterns.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.1349/_p
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@ARTICLE{e93-c_8_1349,
author={Kenta YAMADA, Toshiyuki SYO, Hisao YOSHIMURA, Masaru ITO, Tatsuya KUNIKIYO, Toshiki KANAMOTO, Shigetaka KUMASHIRO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns},
year={2010},
volume={E93-C},
number={8},
pages={1349-1358},
abstract={Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practicality. This paper proposes a methodology and test patterns for exhaustively and systematically validating layout-aware compact models for general layout patterns for the first time. The methodology and test patterns are concretely shown through validation of a shallow trench isolation (STI) stress compact model proposed in [1]. First, the model parameters for a 55-nm CMOS technology are extracted, and then the model is verified and established to be accurate for the basic patterns used for parameter extraction. Next, fundamental ideas of model operation for general layout patterns are verified using various verification patterns. These tests revealed that the model is relatively weak in some cases not included in the basic patterns. Finally, the errors for these cases are eliminated by enhancing the algorithm. Consequently, the model is confirmed to have high generality. This methodology will be effective for validating other layout-aware compact models for general layout patterns.},
keywords={},
doi={10.1587/transele.E93.C.1349},
ISSN={1745-1353},
month={August},}
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TY - JOUR
TI - Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns
T2 - IEICE TRANSACTIONS on Electronics
SP - 1349
EP - 1358
AU - Kenta YAMADA
AU - Toshiyuki SYO
AU - Hisao YOSHIMURA
AU - Masaru ITO
AU - Tatsuya KUNIKIYO
AU - Toshiki KANAMOTO
AU - Shigetaka KUMASHIRO
PY - 2010
DO - 10.1587/transele.E93.C.1349
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2010
AB - Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practicality. This paper proposes a methodology and test patterns for exhaustively and systematically validating layout-aware compact models for general layout patterns for the first time. The methodology and test patterns are concretely shown through validation of a shallow trench isolation (STI) stress compact model proposed in [1]. First, the model parameters for a 55-nm CMOS technology are extracted, and then the model is verified and established to be accurate for the basic patterns used for parameter extraction. Next, fundamental ideas of model operation for general layout patterns are verified using various verification patterns. These tests revealed that the model is relatively weak in some cases not included in the basic patterns. Finally, the errors for these cases are eliminated by enhancing the algorithm. Consequently, the model is confirmed to have high generality. This methodology will be effective for validating other layout-aware compact models for general layout patterns.
ER -