In the hardware synthesis methods with high level languages such as C language, optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers, minimization of the bit length of the data-paths is one of the most important issues. In this paper, we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/data-flow graph translated from C programs and decides the bit length of each variable. On several experiments, the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.

This paper describes an experimental study on resonant properties of the plasma-wave field-effect transistors (PW-FET's). The PW-FET is a new type of the electron devices, which utilizes the plasma resonance effect of highly dense two-dimensional conduction electrons in the FET channel. Frequency tunability of plasma-wave resonance in the terahertz range was experimentally investigated for sub 100-nm gate-length GaAs MESFET's by means of laser-photo-mixing terahertz excitation. The measured results, including the first observation of the third-harmonic resonance in the terahertz range, however, fairly deviate from the ideal characteristics expected for an ideal 2-D confined electron systems. The steady-state electronic charge distribution in the MESFET channel under laser illumination was analyzed to study the effect of insufficient carrier confinement on the frequency tunability. The simulated results support the measured results. It was clarified that an ideal heterostructure 2-D electron confinement is essential to assuring smooth, monotonic frequency tunability of plasma-wave resonance.