IEICE TRANSACTIONS on Fundamentals
Hardware Synthesis from C Programs with Estimation of Bit Length of Variables
Summary :
In the hardware synthesis methods with high level languages such as C language, optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers, minimization of the bit length of the data-paths is one of the most important issues. In this paper, we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/data-flow graph translated from C programs and decides the bit length of each variable. On several experiments, the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.
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- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.11 pp.2338-2346
- Publication Date
- 1999/11/25
- Publicized
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- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Osamu OGAWA, Kazuyoshi TAKAGI, Yasufumi ITOH, Shinji KIMURA, Katsumasa WATANABE, "Hardware Synthesis from C Programs with Estimation of Bit Length of Variables" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2338-2346, November 1999, doi: .
Abstract: In the hardware synthesis methods with high level languages such as C language, optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers, minimization of the bit length of the data-paths is one of the most important issues. In this paper, we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/data-flow graph translated from C programs and decides the bit length of each variable. On several experiments, the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2338/_p
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@ARTICLE{e82-a_11_2338,
author={Osamu OGAWA, Kazuyoshi TAKAGI, Yasufumi ITOH, Shinji KIMURA, Katsumasa WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Hardware Synthesis from C Programs with Estimation of Bit Length of Variables},
year={1999},
volume={E82-A},
number={11},
pages={2338-2346},
abstract={In the hardware synthesis methods with high level languages such as C language, optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers, minimization of the bit length of the data-paths is one of the most important issues. In this paper, we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/data-flow graph translated from C programs and decides the bit length of each variable. On several experiments, the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.},
keywords={},
doi={},
ISSN={},
month={November},}
Copy
TY - JOUR
TI - Hardware Synthesis from C Programs with Estimation of Bit Length of Variables
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2338
EP - 2346
AU - Osamu OGAWA
AU - Kazuyoshi TAKAGI
AU - Yasufumi ITOH
AU - Shinji KIMURA
AU - Katsumasa WATANABE
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - In the hardware synthesis methods with high level languages such as C language, optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers, minimization of the bit length of the data-paths is one of the most important issues. In this paper, we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/data-flow graph translated from C programs and decides the bit length of each variable. On several experiments, the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.
ER -
English
