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[Author] Satoshi YOKOTA(2hit)

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  • Conformance Test of a Logic Synthesis System to the Standard HDL UDL/I

    Satoshi YOKOTA  Hiroyuki KANBARA  

     
    PAPER

      Vol:
    E78-A No:12
      Page(s):
    1742-1748

    This paper presents testing methods for a logic synthesis system which supports the standard HDL UDL/I, focusing on conformance test to the language specification. Conformance test, to prove that the system completely satisfies the language specification, is very important to provide a unified design environment for users of CAD tools which support the language. The basic idea of our testing methods is using a logic simulator, due to a limited schedule for the test execution. We classified the test into two: unit test and integration test. Unit test is a test of each individual functionality of the system, and integration test is a test to prove that the whole system works correctly and satisfies the language specification. And we prepared and used various kinds of test data. One of them is the UDL/I Test Suite and it was also utilized to observe progress of language coverage by the system during the test execution.

  • Validation of UDL/I Test Suites and UDL/I Simulation/Synthesis Environment

    Hiroyuki KANBARA  Satoshi YOKOTA  

     
    PAPER

      Vol:
    E78-A No:12
      Page(s):
    1749-1754

    UDL/I test suites and UDL/I Simulation/Synthesis Environment had been developed separately in parallel. Both were designed from syntax and semantics definition of UDL/I Language Reference Manual. Through test of the UDL/I Simulation/Synthesis Environment using the UDL/I test suites, quality of the test suites and the environment had been improved. Finally all the testing result matched with expected one. It was validated that both the test suites and the environment followed UDL/I language specification.