We present a time-to-digital converter (TDC) achieving sub-picosecond resolution and high precision for all-digital phase-locked-loops (ADPLLs). The basic idea is using a charge pump to translate time interval into charge, and a successive-approximation-register-analog-to-digital converter (SAR-ADC) to quantize the charge. With this less complex configuration, high resolution, high precision, low power, and small area can be achieved all together. We analyzed the noise contribution from the charge pump and describe detailed design and implementation for sizing the capacitor and transistors, with the awareness of noise and linearity. The analysis demonstrates the proposed TDC capable of sub-picosecond resolution and high precision. Two prototype chips were fabricated in 65nm CMOS with 0.06mm2, and 0.018mm2 core areas, respectively. The achieved resolutions are 0.84ps and 0.80ps, in 8-bit and 10-bit range, respectively. The measured single-shot-precisions range from 0.22 to 0.6ps, and from 0.66 to 1.04ps, respectively, showing consistent trends with the analysis. Compared with state-of-the-arts, best performance balance has been achieved.