A method is presented that can substantially reduce the memory requirements of non-binary turbo decoders by efficient representation of the extrinsic information. In the case of the duo-binary turbo decoder employed by the IEEE 802.16e standard, the extrinsic information memory can be reduced by about 43%, which decreases the total decoder complexity by 18%. We also show that the proposed algorithm can be implemented by simple hardware architecture.

A simple address indexing method is proposed for path memory management in multi-PE Viterbi decoder, which solves data read/write conflict problem completely. This method not only simplifies control and addressing overhead but also has the advantage of requiring only two memory banks regardless of the number of PE's, with 100% PE utilization.

Serious BER performance degradation due to finite numeric precision in VLSI implementation of Log-MAP and MAX-Log-MAP decoders where forward state metric is calculated using reverse tracing method, is analyzed, and two methods are proposed to overcome this problem, the loser storing method for MAX-Log-MAP and the periodic storing method for Log-MAP and MAX-Log-MAP. Both methods can reduce memory storage size effectively by half, but with additional circuit overhead. Our VLSI implementation examples show that, compared with original method, both methods give about 15% improvement in area and power consumption with identical BER performance.