This paper presents the implementation of a 3 V low power multi-rate of 156, 622, and 1244 Mbps clock and data recovery circuit (CDR) for optical communications tranceiver using new parallel clock recovery architecture based on dual charge-pump PLL. Designed circuit recovers eight-phase clock signals which are one-eighth frequency of the input signal. While the typical system uses the method that compares the input data with recovered clock, the proposed circuit compares a 1/2-bit delayed input data with the serial data generated by the recovered eight-phase clock signals. The advantage of the circuit is that the implementation is easy, since each sub blocks have one-eighth frequency of the input data signal. Morevover, since the circuit works at one-eighth frequency of the input data, it dissipates less power than conventional CMOS recovery circuit. Simulation results show that this recovery circuit can work with power dissipation of less than 40 mW with a single 3 V supply. All the simulations are based on HYUNDAI 0.65 µm N-Well CMOS double-poly double-metal technology.

The delta-sigma modulator (DSM) is an excellent choice for high-resolution analog-to-digital converters. Recently, a band-pass DSM has been a desirable choice for direct conversion of an IF signal into a digital bit stream. This paper proposes a quadrature band-pass DSM for digitizing a narrow-band IF signal. This modulator can achieve a lower total order, higher signal-to-noise ratio (SNR), and higher bandwidth when compared with conventional band-pass modulators. An experimental prototype employing the quadrature topology has been integrated in 0.6 µm, double-poly, double-metal CMOS technology with capacitors synthesized from a stacked poly structure. This system clocked at 13 MHz and digitized a 200 kHz bandwidth signal centered at 4.875 MHz with 100 dB of dynamic range. Power consumption is 190 mW at 5 V.

This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.