IEICE TRANSACTIONS on Electronics
Design of a Digitally Error-Corrected Pipeline ADC Using Incomplete Settling of Pre-Charged Residue Amplifiers
Summary :
This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E96-C No.6 pp.828-837
- Publication Date
- 2013/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E96.C.828
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Sung-Wook JUN
Shizuoka University
Lianghua MIAO
Shizuoka University
Keita YASUTOMI
Shizuoka University
Keiichiro KAGAWA
Shizuoka University
Shoji KAWAHITO
Shizuoka University
Keyword
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Sung-Wook JUN, Lianghua MIAO, Keita YASUTOMI, Keiichiro KAGAWA, Shoji KAWAHITO, "Design of a Digitally Error-Corrected Pipeline ADC Using Incomplete Settling of Pre-Charged Residue Amplifiers" in IEICE TRANSACTIONS on Electronics,
vol. E96-C, no. 6, pp. 828-837, June 2013, doi: 10.1587/transele.E96.C.828.
Abstract: This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E96.C.828/_p
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@ARTICLE{e96-c_6_828,
author={Sung-Wook JUN, Lianghua MIAO, Keita YASUTOMI, Keiichiro KAGAWA, Shoji KAWAHITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a Digitally Error-Corrected Pipeline ADC Using Incomplete Settling of Pre-Charged Residue Amplifiers},
year={2013},
volume={E96-C},
number={6},
pages={828-837},
abstract={This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.},
keywords={},
doi={10.1587/transele.E96.C.828},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - Design of a Digitally Error-Corrected Pipeline ADC Using Incomplete Settling of Pre-Charged Residue Amplifiers
T2 - IEICE TRANSACTIONS on Electronics
SP - 828
EP - 837
AU - Sung-Wook JUN
AU - Lianghua MIAO
AU - Keita YASUTOMI
AU - Keiichiro KAGAWA
AU - Shoji KAWAHITO
PY - 2013
DO - 10.1587/transele.E96.C.828
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E96-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2013
AB - This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.
ER -
English
