A novel method for the guided-probe diagnosis of high-performance LSIs containing macrocells, which have no internal netlist essential to the diagnosis, has been developed. In this method, the macrocell netlist is derived from its layout by extracting a leaf-cell-level netlist and is combined with the original one. Logic models for the leaf cells in the extracted netlist are also generated to obtain the logic-simulation data in the macrocells. The logic modeling is extended for application to memory macrocells, based on the idea that analog-behavior leaf cells in the memory macrocells are converted into logically equivalent circuits for logic simulation. Specifically, sense amplifiers and wired-or connections on bit lines are replaced with the corresponding logic-behavior models. The proposed method has been successfully applied to actual design data of LSIs containing macrocells, and it has been verified that it enables fault paths inside macrocells to be accurately traced and that the logic models give good timing resolution in the logic simulation. Using the proposed method, LSIs containing macrocells will be able to be diagnosed regardless of the macrocell types, without the need for a "golden" device, by an electron-beam guided probe system.

A novel testing-pad placement method has been developed to greatly improve E-beam observability for multi-level wiring LSIs. In the method, testing pads connecting a lower-metal-layer wire with a top-metal-layer electrode are positioned in the design layout, making removal of the insulator unnecessary. The method features i) pad placement in unoccupied areas in mask patterns to avoid increases in chip size, ii) minimized pad size through the use of stacked vias so that the pads can be placed on as many wire nodes as possible, iii) placement as far as possible from the nearby wires to avoid local field effects, and iv) allocation of one testing pad to one circuit node to minimize the number of testing pads. These measures give us a practical pad-placement method, that has little influence on LSI design. It was shown that the proposed method yielded a dramatic improvement of observability from 13-33% to 88-99% in actual layouts of 0.25-µm ASICs with 20k, 120k, and 390k gates. It was also found that local field effects from nearby wires are negligible for almost all the testing pads. This approach will enable the use of E-beam testing on LSIs made with 0.25-µm technology and the even more sophisticated process technologies to come.

An on-line scheduler for ASIC manufacturing line management has been developed. The parameters in the schedule models and the dynamic priority curve in the schedule algorithm were adjusted to obtain schedules well-suited to practical ASIC line management and control. The scheduler is connected to the user interface control module of our ASIC CIM system. In order to facilitate on-line scheduling, we clarify the performance requirements of the computer used for the scheduler with respect to the line scale. Using a current EWS, the scheduler can easily make a one-day schedule for a small-scale line with an annual throughput of less than 1,000 lots within 10 minutes. To cope with larger-scale lines, the multiple scheduling method allows schedules to be produced quickly and efficiently. Therefore, the scheduler can respond flexibly to changes in production plan and line resources and the control delivery date of each lot.

A detabase system that provides step-by-step guidance for LSI failure analysts has been developed. This system has three main functions: database, navigator, and chip tracking. The datebase stores failure analysis information such as analysis method and failure mechanisms including image data. It also stores conditions and results of each analysis step and decisions to proceeds to the next analysis step. With 2000 failure analysis cases, data retrieval takes 6.6 seconds, a table containing 20 photos is presented in 6.5 seconds, and a different set of data can be displayed in 0.6 seconds. The navigator displays a standard analysis procedure illustrated in flow charts.The chip tracking shows where the particular chip is and what analysis it is undergoing, which is useful for the situation where many chips are simultaneously analyzed. Thus, this system has good enough functions of analysis procedure management and performance of quick data access to make failure analysis easier and more successful.