Power consumption has become an increasing concern in high performance microprocessor design. Especially, Instruction Cache (I-Cache) contributes a large portion of the total power consumption in a microprocessor, since it is a complex unit and is accessed very frequently. Several studies on low-power design have been presented for the power-efficient cache design. However, these techniques usually suffer from the restrictions in the traditional Instruction Fetch Unit (IFU) architectures where the fetch address needs to be sent to I-Cache once it is available. Therefore, work to reduce the power consumption is limited after the address generation and before starting an access. In this paper, we present a new power-aware IFU architecture, named Analysis Before Starting an Access (ABSA), which aims at maximizing the power efficiency of the low-power designs by eliminating the restrictions on those low-power designs of the traditional IFU. To achieve this goal, ABSA reorganizes the IFU pipeline and carefully assigns tasks for each stages so that sufficient time and information can be provided for the low-power techniques to maximize the power efficiency before starting an access. The proposed design is fully scalable and its cost is low. Compared to a conventional IFU design, simulation results show that ABSA saves about 30.3% fetch power consumption, on average. I-Cache employed by ABSA reduces both static and dynamic power consumptions about 85.63% and 66.92%, respectively. Meanwhile the performance degradation is only about 0.97%.

A 19.1-to-20.4 GHz sigma-delta fractional-N frequency synthesizer with two-point modulation (TPM) for frequency modulated continuous wave (FMCW) radar applications is presented. The FMCW synthesizer proposes a digital and voltage controlled oscillator (D/VCO) with large continuous frequency tuning range and small digital controlled oscillator (DCO) gain variation to support TPM. By using TPM technique, it avoids the correlation between loop bandwidth and chirp slope, which is beneficial to fast chirp, phase noise and linearity. The start frequency, bandwidth and slope of the FMCW signal are all reconfigurable independently. The FMCW synthesizer achieves a measured phase noise of -93.32 dBc/Hz at 1MHz offset from a 19.25 GHz carrier and less than 10 µs locking time. The root-mean-square (RMS) frequency error is only 112 kHz with 94 kHz/µs chirp slope, and 761 kHz with a fast slope of 9.725 MHz/µs respectively. Implemented in 65 nm CMOS process, the synthesizer consumes 74.3 mW with output buffer.

A major challenge in wideband spectrum sensing, in cognitive radio system for example, is the requirement of a high sampling rate which may exceed today's best analog-to-digital converters (ADCs) front-end bandwidths. Compressive sampling is an attractive way to reduce the sampling rate. The modulated wideband converter (MWC) proposed recently is one of the most successful compressive sampling hardware architectures, but it has high hardware complexity owing to its parallel channels structure. In this paper, we design a single channel sub-Nyquist sampling scheme to bring substantial savings in terms of not only sampling rate but also hardware complexity, and we also present a wideband power spectrum sensing and reconstruction method for bandlimited wide-sense stationary (WSS) signals. The total sampling rate is only one channel rate of the MWC's. We evaluate the performance of the sensing model by computing the probability of detecting signal occupancy in terms of the signal-to-noise ratio (SNR) and other practical parameters. Simulation results underline the promising performance of proposed approach.

Automatic modulation recognition (AMR) plays a critical role in modern communication systems. Owing to the recent advancements of deep learning (DL) techniques, the application of DL has been widely studied in AMR, and a large number of DL-AMR algorithms with high recognition rates have been developed. Most DL-AMR algorithm models have high recognition accuracy but have numerous parameters and are huge, complex models, which make them hard to deploy on resource-constrained platforms, such as satellite platforms. Some lightweight and low-complexity DL-AMR algorithm models also struggle to meet the accuracy requirements. Based on this, this paper proposes a lightweight and high-recognition-rate DL-AMR algorithm model called Lightweight Densely Connected Convolutional Network (DenseNet) Long Short-Term Memory network (LDLSTM). The model cascade of DenseNet and LSTM can achieve the same recognition accuracy as other advanced DL-AMR algorithms, but the parameter volume is only 1/12 that of these algorithms. Thus, it is advantageous to deploy LDLSTM in resource-constrained systems.

We investigate linear complementary dual (LCD) rank-metric codes in this paper. We construct a class of LCD generalized Gabidulin codes by a self-dual basis of an extension field over the base field. Moreover, a class of LCD MRD codes, which are obtained by Cartesian products of a generalized Gabidulin code, is constructed.

We propose a new associative memory named Multi-Winner Associative Memory (MWAM) and study its bidirectional association properties in this paper. The proposed MWAM has two processes for pattern pairs storage: storage process and recall process. For the storage process, the proposed MWAM can represent a half of pattern pair in the distributed representation layer and can store the correspondence of pattern and its representation using the upward weights. In addition, the MWAM can store the correspondence of the distributed representation and the other half of pattern pair in the downward weights. For the recall process, the MWAM can recall information bidirectionally: a half of the stored pattern pair can be recalled by receiving the other half in the input-output layer for any stored pattern pairs.