In this letter, we study the performance of multi-antenna relay networks with limited feedback beamforming in decode-and-forward (DF) relaying. Closed-form expression for both outage probability and symbol error rate are derived by using the moment generation function (MGF) of the combined signal-to-noise ratio (SNR) at the destination. Subjected to a total power constraint, we also explore adaptive power allocation between source and relay to optimize the performance. Simulations are given to verify the correctness of our theoretical derivations. Results show that the proposed adaptive power allocation solution significantly outperforms the uniform power allocation method.

This paper presents a novel test data compression scheme for SoCs based on block merging and compatibility. The technique exploits the properties of compatibility and inverse compatibility between consecutive blocks, consecutive merged blocks, and two halves of the encoding merged block itself to encode the pre-computed test data. The decompression circuit is simple to be implemented and has advantage of test-independent. In addition, the proposed scheme is applicable for IP cores in SoCs since it compresses the test data without requiring any structural information of the circuit under test. Experimental results demonstrate that the proposed technique can achieve an average compression ratio up to 68.02% with significant low test application time.

The quality of edge detection is related to detection angle, scale, and threshold. There have been many algorithms to promote edge detection quality by some rules about detection angles. However these algorithm did not form rules to detect edges at an arbitrary angle, therefore they just used different number of angles and did not indicate optimized number of angles. In this paper, a novel edge detection algorithm is proposed to detect edges at arbitrary angles and optimized number of angles in the algorithm is introduced. The algorithm combines singularity detection with Gaussian wavelet transform and edge detection at arbitrary directions and contain five steps: 1) An image is divided into some pixel lines at certain angle in the range from 45° to 90° according to decomposition rules of this paper. 2) Singularities of pixel lines are detected and form an edge image at the certain angle. 3) Many edge images at different angles form a final edge images. 4) Detection angles in the range from 45° to 90° are extended to range from 0° to 360°. 5) Optimized number of angles for the algorithm is proposed. Then the algorithm with optimized number of angles shows better performances.

Orthogonal frequency division multiplexing (OFDM) signals have high peak-to-average power ratio (PAPR) and cause large nonlinear distortions in power amplifiers (PAs). Memory effects in PAs also become no longer ignorable for the wide bandwidth of OFDM signals. Digital baseband predistorter is a highly efficient technique to compensate the nonlinear distortions. But it usually has many parameters and takes long time to converge. This paper presents a novel predistorter design using a set of orthogonal polynomials to increase the convergence speed and the compensation quality. Because OFDM signals are approximately complex Gaussian distributed, the complex Hermite polynomials which have a closed-form expression can be used as a set of orthogonal polynomials for OFDM signals. A differential envelope model is adopted in the predistorter design to compensate nonlinear PAs with memory effects. This model is superior to other predistorter models in parameter number to calculate. We inspect the proposed predistorter performance by using an OFDM signal referred to the IEEE 802.11a WLAN standard. Simulation results show that the proposed predistorter is efficient in compensating memory PAs. It is also demonstrated that the proposal acquires a faster convergence speed and a better compensation effect than conventional predistorters.

Nonlinear distortions in power amplifiers (PAs) generate spectral regrowth at the output, which causes interference to adjacent channels and errors in digitally modulated signals. This paper presents a novel method to evaluate adjacent channel leakage power ratio (ACPR) and error vector magnitude (EVM) from the amplitude-to-amplitude (AM/AM) and amplitude-to-phase (AM/PM) characteristics. The transmitted signal is considered to be complex Gaussian distributed in orthogonal frequency-division multiplexing (OFDM) systems. We use the Mehler formula to derive closed-form expressions of the PAs output power spectral density (PSD), ACPR and EVM for memoryless PA and memory PA respectively. We inspect the derived relationships using an OFDM signal in the IEEE 802.11a WLAN standard. Simulation results show that the proposed method is appropriate to predict the ACPR and EVM values of the nonlinear PA output in OFDM systems, when the AM/AM and AM/PM characteristics are known.

Many software development teams usually tend to focus on maintenance activities in general. Recently, many studies on bug severity prediction have been proposed to help a bug reporter determine severity. But they do not consider the reporter's expression of emotion appearing in the bug report when they predict the bug severity level. In this paper, we propose a novel approach to severity prediction for reported bugs by using emotion similarity. First, we do not only compute an emotion-word probability vector by using smoothed unigram model (UM), but we also use the new bug report to find similar-emotion bug reports with Kullback-Leibler divergence (KL-divergence). Then, we introduce a new algorithm, Emotion Similarity (ES)-Multinomial, which modifies the original Naïve Bayes Multinomial algorithm. We train the model with emotion bug reports by using ES-Multinomial. Finally, we can predict the bug severity level in the new bug report. To compare the performance in bug severity prediction, we select related studies including Emotion Words-based Dictionary (EWD)-Multinomial, Naïve Bayes Multinomial, and another study as baseline approaches in open source projects (e.g., Eclipse, GNU, JBoss, Mozilla, and WireShark). The results show that our approach outperforms the baselines, and can reflect reporters' emotional expressions during the bug reporting.

High-performance FFT processor is indispensable for real-time OFDM communication systems. This paper presents a CORDIC based design of variable-length FFT processor which can perform various FFT lengths of 64/128/256/512/1024/2048/4096/8192-point. The proposed FFT processor employs memory based architecture in which mixed radix 4/2 algorithm, pipelined CORDIC, and conflict-free parallel memory access scheme are exploited. Besides, the CORDIC rotation angles are generated internally based on the transform of butterfly counter, which eliminates the need of ROM making it memory-efficient. The proposed architecture has a lower hardware complexity because it is ROM-free and with no dedicated complex multiplier. We implemented the proposed FFT processor and verified it on FPGA development platform. Additionally, the processor is also synthesized in 0.18 µm technology, the core area of the processor is 3.47 mm2 and the maximum operating frequency can be up to 500 MHz. The proposed FFT processor is better trade off performance and hardware overhead, and it can meet the speed requirement of most modern OFDM system, such as IEEE 802.11n, WiMax, 3GPP-LTE and DVB-T/H.

The properties of the surface-conduction electron-emitter display (SED) are mainly decided by the surface-conduction electron emitters (SCE), which are normally made from the expensive metal Pd. In this study, we propose to use metal Zn instead of Pd as the emitter material. Both the device electrode and ZnO thin film are deposited by a sputter, and the electron emitters (SCE) are formed by the electro-forming process. The electron emission characteristic is obtained and the luminescence is observed.

The adaptive predistorter and the negative feedback system are known as methods to compensate for the nonlinear distortion of a power amplifier. Although the feedback method is a simple technique, its instability impedes the capability of high-feedback gain to achieve a high-compensation effect. On the other hand, the predistorter requires a long time for convergence of the adaptive predistorters. In this paper, we propose a nonlinear distortion compensation method for a narrow-band signal. In this method, an adaptive predistorter and negative feedback are combined. In addition, to shorten the convergence time to minimize nonlinear distortion, a variable step-size (VS) method is also applied to the algorithm to determine the parameters of the adaptive predistorter. Using computer simulations, we show that the proposed scheme achieves both five times faster convergence speed than that of the predistorter and three times higher permissible delay time in the feedback amplifier than that of a negative feedback only amplifier.

In a real-time system, tasks are required to be completed before their deadlines. Under normal workload conditions, a scheduler with a proper scheduling policy can make all the tasks meet their deadlines. However, in practical environment, system workload may vary widely. Once system workload becomes too heavy, so that there does not exist a feasible schedule can make all the tasks meet their deadlines, we say the system is overloaded under which some tasks will miss their deadlines. To alleviate the degrees of system performance degradation caused by the missed deadline tasks, the design of scheduling is crucial. Many design objectives can be considered. In this paper, we first focus on maximizing the total number of tasks that can be completed before their deadlines. A scheduling method based on satisfiability modulo theories (SMT) is proposed. In the method, the problem of scheduling is treated as a satisfiability problem. The key work is to formalize the satisfiability problem using first-order language. After the formalization, a SMT solver (e.g., Z3, Yices) is employed to solve this satisfiability problem. An optimal schedule can be generated based on the solution model returned by the SMT solver. The correctness of this method and the optimality of the generated schedule can be verified in a straightforward manner. The time efficiency of the proposed method is demonstrated through various simulations. Moreover, in the proposed SMT-based scheduling method, we define the scheduling constraints as system constraints and target constraints. This means if we want to design scheduling to achieve other objectives, only the target constraints need to be modified. To demonstrate this advantage, we adapt the SMT-based scheduling method to other design objectives: maximizing effective processor utilization and maximizing obtained values of completed tasks. Only very little changes are needed in the adaption procedure, which means the proposed SMT-based scheduling method is flexible and sufficiently general.

OSEK/VDX, a standard for an automobile OS, has been widely adopted by many manufacturers to design and develop a vehicle-mounted OS. With the increasing functionalities in vehicles, more and more complex applications are be developed based on the OSEK/VDX OS. However, how to ensure the reliability of developed applications is becoming a challenge for developers. To ensure the reliability of developed applications, model checking as an exhaustive technique can be applied to discover subtle errors in the development process. Many model checkers have been successfully applied to verify sequential software and general multi-threaded software. However, it is hard to directly use existing model checkers to precisely verify OSEK/VDX applications, since the execution characteristics of OSEK/VDX applications are different from the sequential software and general multi-threaded software. In this paper, we describe and develop an approach to translate OSEK/VDX applications into sequential programs in order to employ existing model checkers to precisely verify OSEK/VDX applications. The value of our approach is that it can be considered as a front-end translator for enabling existing model checkers to verify OSEK/VDX applications.

Software products are increasingly complex, so it is becoming more difficult to find and correct bugs in large programs. Software developers rely on bug reports to fix bugs; thus, bug-tracking tools have been introduced to allow developers to upload, manage, and comment on bug reports to guide corrective software maintenance. However, the very high frequency of duplicate bug reports means that the triagers who help software developers in eliminating bugs must allocate large amounts of time and effort to the identification and analysis of these bug reports. In addition, classifying bug reports can help triagers arrange bugs in categories for the fixers who have more experience for resolving historical bugs in the same category. Unfortunately, due to a large number of submitted bug reports every day, the manual classification for these bug reports increases the triagers' workload. To resolve these problems, in this study, we develop a novel technique for automatic duplicate detection and classification of bug reports, which reduces the time and effort consumed by triagers for bug fixing. Our novel technique uses a support vector machine to check whether a new bug report is a duplicate. The concept profile is also used to classify the bug reports into related categories in a taxonomic tree. Finally, we conduct experiments that demonstrate the feasibility of our proposed approach using bug reports extracted from the large-scale open source project Mozilla.

Direction of arrival (DOA) estimation has been a primary focus of research for many years. Research on DOA estimation continues to be immensely popular in the fields of the internet of things, radar, and smart driving. In this paper, a simple new two-dimensional DOA framework is proposed in which a triangular array is used to receive wideband linear frequency modulated continuous wave signals. The mixed echo signals from various targets are separated into a series of single-tone signals. The unwrapping algorithm is applied to the phase difference function of the single-tone signals. By using the least-squares method to fit the unwrapped phase difference function, the DOA information of each target is obtained. Theoretical analysis and simulation demonstrate that the framework has the following advantages. Unlike traditional phase goniometry, the framework can resolve the trade-off between antenna spacing and goniometric accuracy. The number of detected targets is not limited by the number of antennas. Moreover, the framework can obtain highly accurate DOA estimation results.

Data exchange, in which two blocks of data are swapped between cores in distributed memory systems, necessitates additional memory buffer in a multiprocessor system-on-chip. In this paper, we propose a novel bidirectional inter-core communication mechanism called coherent direct memory access (CoDMA). The CoDMA ensures that the writing address is always less than the reading address in coherent read and write mode, so as to avoid read-after-write (RAW) errors. It features an efficient data exchanging scheme without using data buffer in the memory. A four-core single-instruction multiple-data processor is established for the experiments, based on a multi-bus network-on-chip. Experimental results show that the proposed method consumes no additional memory buffer and achieves 39% and 20% average performance improvement compared with traditional Methods 1 and 2, respectively. And a maximal of 43% reduction in memory usage is achieved, at the cost of only 0.22% more area overhead compared with the entire system.

Multi-agent based simulation has been widely used in behavior finance, and several single-processed simulation platforms with Agent-Based Modeling (ABM) have been proposed. However, traditional simulations of stock markets on single processed computers are limited by the computing capability since financial researchers need larger and larger number of agents and more and more rounds to evolve agents' intelligence and get more efficient data. This paper introduces a distributed multi-agent simulation platform, named PSSPAM, for stock market simulation focusing on large scale of parallel agents, communication system and simulation scheduling. A logical architecture for distributed artificial stock market simulation is proposed, containing four loosely coupled modules: agent module, market module, communication system and user interface. With the customizable trading strategies inside, agents are deployed to multiple computing nodes. Agents exchange messages with each other and with the market based on a customizable network topology through a uniform communication system. With a large number of agent threads, the round scheduling strategy is used during the simulation, and a worker pool is applied in the market module. Financial researchers can design their own financial models and run the simulation through the user interface, without caring about the complexity of parallelization and related problems. Two groups of experiments are conducted, one with internal communication between agents and the other without communication between agents, to verify PSSPAM to be compatible with the data from Euronext-NYSE. And the platform shows fair scalability and performance under different parallelism configurations.