In this paper, a lifting implementation of variable-coefficient invertible deinterlacer with embedded motion detector is proposed. As previous works, the authors have developed invertible deinterlacing that suppresses comb-tooth artifacts caused by field interleaving for interlaced scanning video, which affect the quality of intraframe-based codec such as Motion-JPEG2000. To improve the local adaptability for given pictures, its variable-coefficient processing with motion detection has also been proposed so that filters can be changed according to local properties of motion pictures, while maintaining the invertibility. In this paper, it is shown that the variable-coefficient invertible deinterlacing can be realized by a lifting-based simple hardware architecture, and motion detector can also be embedded. Both of the motion detection and deinterlacing filters are shared by a special choice of their coefficients, and by adaptive selection of deinterlacing filters. The significance of our proposed architecture is verified by showing synthesis results from the VHDL models. The proposed implementation with embedded motion detector achieves about 28% reduction of the gate count compared with the corresponding separate implementation.

Several lifting implementation techniques for invertible deniterlacing are proposed in this paper. Firstly, the invertible deinterlacing is reviewed, and an efficient implementation is presented. Next, two deinterlacer-embedded lifting architectures of discrete wavelet transforms (DWT) is proposed. Performances are compared among several architectures of deinterlacing with DWT. The performance evaluation includes dual-multiplier and single-multiplier architectures. The number of equivalent gates shows that the deinterlacing-embedded architectures require less resources than the separate implementaion. Our experimental evaluation of the dual-multiplier architecture results in 0.8% increase in the gate count, whereas the separate implementation of deinterlacing and DWT requires 6.1% increase from the normal DWT architecture. For the proposed single-multiplier architecture, the gate count is shown to result in 4.5% increase, while the separate counterpart yields 10.7% increase.