IEICE TRANSACTIONS on Fundamentals
Lifting Architecture of Invertible Deinterlacing
Summary :
Several lifting implementation techniques for invertible deniterlacing are proposed in this paper. Firstly, the invertible deinterlacing is reviewed, and an efficient implementation is presented. Next, two deinterlacer-embedded lifting architectures of discrete wavelet transforms (DWT) is proposed. Performances are compared among several architectures of deinterlacing with DWT. The performance evaluation includes dual-multiplier and single-multiplier architectures. The number of equivalent gates shows that the deinterlacing-embedded architectures require less resources than the separate implementaion. Our experimental evaluation of the dual-multiplier architecture results in 0.8% increase in the gate count, whereas the separate implementation of deinterlacing and DWT requires 6.1% increase from the normal DWT architecture. For the proposed single-multiplier architecture, the gate count is shown to result in 4.5% increase, while the separate counterpart yields 10.7% increase.
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- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.4 pp.779-786
- Publication Date
- 2003/04/01
- Publicized
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- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
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Tatsuumi SOYAMA, Takuma ISHIDA, Shogo MURAMATSU, Hisakazu KIKUCHI, Tetsuro KUGE, "Lifting Architecture of Invertible Deinterlacing" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 4, pp. 779-786, April 2003, doi: .
Abstract: Several lifting implementation techniques for invertible deniterlacing are proposed in this paper. Firstly, the invertible deinterlacing is reviewed, and an efficient implementation is presented. Next, two deinterlacer-embedded lifting architectures of discrete wavelet transforms (DWT) is proposed. Performances are compared among several architectures of deinterlacing with DWT. The performance evaluation includes dual-multiplier and single-multiplier architectures. The number of equivalent gates shows that the deinterlacing-embedded architectures require less resources than the separate implementaion. Our experimental evaluation of the dual-multiplier architecture results in 0.8% increase in the gate count, whereas the separate implementation of deinterlacing and DWT requires 6.1% increase from the normal DWT architecture. For the proposed single-multiplier architecture, the gate count is shown to result in 4.5% increase, while the separate counterpart yields 10.7% increase.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_4_779/_p
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@ARTICLE{e86-a_4_779,
author={Tatsuumi SOYAMA, Takuma ISHIDA, Shogo MURAMATSU, Hisakazu KIKUCHI, Tetsuro KUGE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Lifting Architecture of Invertible Deinterlacing},
year={2003},
volume={E86-A},
number={4},
pages={779-786},
abstract={Several lifting implementation techniques for invertible deniterlacing are proposed in this paper. Firstly, the invertible deinterlacing is reviewed, and an efficient implementation is presented. Next, two deinterlacer-embedded lifting architectures of discrete wavelet transforms (DWT) is proposed. Performances are compared among several architectures of deinterlacing with DWT. The performance evaluation includes dual-multiplier and single-multiplier architectures. The number of equivalent gates shows that the deinterlacing-embedded architectures require less resources than the separate implementaion. Our experimental evaluation of the dual-multiplier architecture results in 0.8% increase in the gate count, whereas the separate implementation of deinterlacing and DWT requires 6.1% increase from the normal DWT architecture. For the proposed single-multiplier architecture, the gate count is shown to result in 4.5% increase, while the separate counterpart yields 10.7% increase.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - Lifting Architecture of Invertible Deinterlacing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 779
EP - 786
AU - Tatsuumi SOYAMA
AU - Takuma ISHIDA
AU - Shogo MURAMATSU
AU - Hisakazu KIKUCHI
AU - Tetsuro KUGE
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 2003
AB - Several lifting implementation techniques for invertible deniterlacing are proposed in this paper. Firstly, the invertible deinterlacing is reviewed, and an efficient implementation is presented. Next, two deinterlacer-embedded lifting architectures of discrete wavelet transforms (DWT) is proposed. Performances are compared among several architectures of deinterlacing with DWT. The performance evaluation includes dual-multiplier and single-multiplier architectures. The number of equivalent gates shows that the deinterlacing-embedded architectures require less resources than the separate implementaion. Our experimental evaluation of the dual-multiplier architecture results in 0.8% increase in the gate count, whereas the separate implementation of deinterlacing and DWT requires 6.1% increase from the normal DWT architecture. For the proposed single-multiplier architecture, the gate count is shown to result in 4.5% increase, while the separate counterpart yields 10.7% increase.
ER -
English
