In most of the voltage-mode CMOS-multiple-valued-logic circuits published so far, distinct voltage levels are used for the logic values and the logical operations are carried out by binary circuits through converting once multiple-valued imputs to binary signals. In this case, encoder circuits are employed for the multiple-valued outputs. Such voltage-mode circuits are not always competitive with binary circuits except for the reduced number of pins for IC realization. In this letter, new CMOS logical-sum (Max) and logical-product (Min) circuits which can perform directly multiple-valued-logic operations without converting multiple-valued inputs to binary signals are presented. As the proposed circuits have the same property of low-power dissipation as usual CMOS inverters, they are suited for binary circuit use as well. In two-input case, each of the logical-sum and logical-product circuits is composed of a pair of PMOS and NMOS transistors and, except for the number of inputs and the circuit-function, the circuit configuration is the same as that introduced by Sugano, Tarui and Asada. The transient characteristics of the proposed circuits obtained by SPICE-2 simulations are shown. In this letter, logical values 0, 1, 2, and 3 are represented by voltage levels 0 V, 2 V, 4 V and 6 V respectively.