IEICE TRANSACTIONS on transactions
Logical-Sum and Logical-Product Circuits Using CMOS Transistors for Binary and Multiple-Valued Logics
Summary :
In most of the voltage-mode CMOS-multiple-valued-logic circuits published so far, distinct voltage levels are used for the logic values and the logical operations are carried out by binary circuits through converting once multiple-valued imputs to binary signals. In this case, encoder circuits are employed for the multiple-valued outputs. Such voltage-mode circuits are not always competitive with binary circuits except for the reduced number of pins for IC realization. In this letter, new CMOS logical-sum (Max) and logical-product (Min) circuits which can perform directly multiple-valued-logic operations without converting multiple-valued inputs to binary signals are presented. As the proposed circuits have the same property of low-power dissipation as usual CMOS inverters, they are suited for binary circuit use as well. In two-input case, each of the logical-sum and logical-product circuits is composed of a pair of PMOS and NMOS transistors and, except for the number of inputs and the circuit-function, the circuit configuration is the same as that introduced by Sugano, Tarui and Asada. The transient characteristics of the proposed circuits obtained by SPICE-2 simulations are shown. In this letter, logical values 0, 1, 2, and 3 are represented by voltage levels 0 V, 2 V, 4 V and 6 V respectively.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E70-E No.4 pp.367-369
- Publication Date
- 1987/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Issue: Papers from 1987 National Convention IEICE)
- Category
- Instrumentation and Electronic Circuits
Authors
Keyword
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Tatsuki WATANABE, Masayuki MATSUMOTO, Tekken LI, "Logical-Sum and Logical-Product Circuits Using CMOS Transistors for Binary and Multiple-Valued Logics" in IEICE TRANSACTIONS on transactions,
vol. E70-E, no. 4, pp. 367-369, April 1987, doi: .
Abstract: In most of the voltage-mode CMOS-multiple-valued-logic circuits published so far, distinct voltage levels are used for the logic values and the logical operations are carried out by binary circuits through converting once multiple-valued imputs to binary signals. In this case, encoder circuits are employed for the multiple-valued outputs. Such voltage-mode circuits are not always competitive with binary circuits except for the reduced number of pins for IC realization. In this letter, new CMOS logical-sum (Max) and logical-product (Min) circuits which can perform directly multiple-valued-logic operations without converting multiple-valued inputs to binary signals are presented. As the proposed circuits have the same property of low-power dissipation as usual CMOS inverters, they are suited for binary circuit use as well. In two-input case, each of the logical-sum and logical-product circuits is composed of a pair of PMOS and NMOS transistors and, except for the number of inputs and the circuit-function, the circuit configuration is the same as that introduced by Sugano, Tarui and Asada. The transient characteristics of the proposed circuits obtained by SPICE-2 simulations are shown. In this letter, logical values 0, 1, 2, and 3 are represented by voltage levels 0 V, 2 V, 4 V and 6 V respectively.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e70-e_4_367/_p
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@ARTICLE{e70-e_4_367,
author={Tatsuki WATANABE, Masayuki MATSUMOTO, Tekken LI, },
journal={IEICE TRANSACTIONS on transactions},
title={Logical-Sum and Logical-Product Circuits Using CMOS Transistors for Binary and Multiple-Valued Logics},
year={1987},
volume={E70-E},
number={4},
pages={367-369},
abstract={In most of the voltage-mode CMOS-multiple-valued-logic circuits published so far, distinct voltage levels are used for the logic values and the logical operations are carried out by binary circuits through converting once multiple-valued imputs to binary signals. In this case, encoder circuits are employed for the multiple-valued outputs. Such voltage-mode circuits are not always competitive with binary circuits except for the reduced number of pins for IC realization. In this letter, new CMOS logical-sum (Max) and logical-product (Min) circuits which can perform directly multiple-valued-logic operations without converting multiple-valued inputs to binary signals are presented. As the proposed circuits have the same property of low-power dissipation as usual CMOS inverters, they are suited for binary circuit use as well. In two-input case, each of the logical-sum and logical-product circuits is composed of a pair of PMOS and NMOS transistors and, except for the number of inputs and the circuit-function, the circuit configuration is the same as that introduced by Sugano, Tarui and Asada. The transient characteristics of the proposed circuits obtained by SPICE-2 simulations are shown. In this letter, logical values 0, 1, 2, and 3 are represented by voltage levels 0 V, 2 V, 4 V and 6 V respectively.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Logical-Sum and Logical-Product Circuits Using CMOS Transistors for Binary and Multiple-Valued Logics
T2 - IEICE TRANSACTIONS on transactions
SP - 367
EP - 369
AU - Tatsuki WATANABE
AU - Masayuki MATSUMOTO
AU - Tekken LI
PY - 1987
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E70-E
IS - 4
JA - IEICE TRANSACTIONS on transactions
Y1 - April 1987
AB - In most of the voltage-mode CMOS-multiple-valued-logic circuits published so far, distinct voltage levels are used for the logic values and the logical operations are carried out by binary circuits through converting once multiple-valued imputs to binary signals. In this case, encoder circuits are employed for the multiple-valued outputs. Such voltage-mode circuits are not always competitive with binary circuits except for the reduced number of pins for IC realization. In this letter, new CMOS logical-sum (Max) and logical-product (Min) circuits which can perform directly multiple-valued-logic operations without converting multiple-valued inputs to binary signals are presented. As the proposed circuits have the same property of low-power dissipation as usual CMOS inverters, they are suited for binary circuit use as well. In two-input case, each of the logical-sum and logical-product circuits is composed of a pair of PMOS and NMOS transistors and, except for the number of inputs and the circuit-function, the circuit configuration is the same as that introduced by Sugano, Tarui and Asada. The transient characteristics of the proposed circuits obtained by SPICE-2 simulations are shown. In this letter, logical values 0, 1, 2, and 3 are represented by voltage levels 0 V, 2 V, 4 V and 6 V respectively.
ER -
English
