This paper introduces a new digital ATC (Automatic Train Control device) system. In the current ATC, the central ATC logic device calculates permissive speed of each blocking section and controls speed of all trains. On the other hand, in the new digital ATC, the central logic controller calculates each position to which a train can move safely, and sends the information on positions to all trains. On each train, the on-board equipment calculates an appropriate braking pattern with the information, and controls velocity of the train. That is, in the new system, the device on each train autonomously calculates permissive speed of that train. These special features realize ideal speed control of each train making full use of its performance for acceleration and deceleration, which in turns allows high-density train operations.

We have developed a novel railway signal control system that operates as a distributed system. It consists of a central control unit (called LC) and terminal devices (called FC) that are distributed at the railroad wayside and operate signal devices. The Internet technologies and optical LAN technologies have been used as communication methods between the LC and the FCs. While handling enormous amount of electric cables may cause human errors, the system is expected to reduce troubles of the current signal system at construction works thanks to the Internet technologies. The FC is a distributed terminal device that has its own processor and placed at the railroad wayside to control the field signal devices. The LC is a centralized computer device that has software arranged by the function of the field devices. An optical network system and multiple communication paths between the LC and the FCs realize durable transmissions. Moreover, the assure performance of controls and transmissions have been investigated, and the autonomous distributed signal control system is also discussed as the next steps of the system.

We experimentally demonstrated polarization-mode dispersion (PMD) compensation by distributing polarizers with only 1 degree of freedom (DOF) along the transmission line. The average power penalty was measured to be 0.4 dB by inserting four compensators, where average differential group delay was 47% of bit period.

In most of the voltage-mode CMOS-multiple-valued-logic circuits published so far, distinct voltage levels are used for the logic values and the logical operations are carried out by binary circuits through converting once multiple-valued imputs to binary signals. In this case, encoder circuits are employed for the multiple-valued outputs. Such voltage-mode circuits are not always competitive with binary circuits except for the reduced number of pins for IC realization. In this letter, new CMOS logical-sum (Max) and logical-product (Min) circuits which can perform directly multiple-valued-logic operations without converting multiple-valued inputs to binary signals are presented. As the proposed circuits have the same property of low-power dissipation as usual CMOS inverters, they are suited for binary circuit use as well. In two-input case, each of the logical-sum and logical-product circuits is composed of a pair of PMOS and NMOS transistors and, except for the number of inputs and the circuit-function, the circuit configuration is the same as that introduced by Sugano, Tarui and Asada. The transient characteristics of the proposed circuits obtained by SPICE-2 simulations are shown. In this letter, logical values 0, 1, 2, and 3 are represented by voltage levels 0 V, 2 V, 4 V and 6 V respectively.