The memory issue plays a very important role for the performance evaluation of a design of 2-Dimensional Discrete Wavelet Transform (2DDWT). A traditional 2DDWT architecture generally needs DRAM to store the input pixel and memory to store temporary results between the row and column processors. In this article, we present a system on a chip (SoC) for video/image processing. The chip integrates an analog-to-digital converter (ADC) with a highly efficient-memory 2DDWT. The latter one contains two main components only: a row processor and a column processor. With this integrated chip plus the use of feedback shift registers (FSR) in the column processor, the architecture we propose can disuse the DRAM and reduce the memory. The pipelined technique is also utilized in the proposed 2DDWT to shorten the critical path to an adder delay. Our architecture outperforms the existing architectures in that it uses less memory size and has low control complexity. It needs only a 2N register instead of a 3.5N register of traditional architectures for a one-level 2DDWT of the 5/3 Lifting-based Discrete Wavelet Transform (LDWT) in an N x N image. Our 2DDWT architecture is coded in VerilogHDL and the Synopsys Design Compiler is employed to synthesize the design with the standard-cell from TSMC 0.18 µm cell library for verification. The ADC is designed by a full-custom methodology, plays as an IP of the SoC. With the integrated SoC, based on the mix-mode design flow, the proposed work requires no external memory, which accordingly reduces the power consumption by memory access and 20 I/O PADs, it also reduces the printed circuit board (PCB) size. Moreover, the proposed SoC supports the resolution of 10 bits and can easily integrate further with the CMOS image sensor (CIS) or other IPs. This, then, completes a single chip and which is ready for a real-time wavelet-based video coding.

With the development of digital TV system, how to display the NTSC signal in digital TV system is a problem. De-interlacing is an algorithm to solve it. In previous papers, using motion compensation (MC) method for de-interlacing needs lots of computation complexity and it is not easy to implement in hardware. In this paper, a content adaptive de-interlacing algorithm is proposed. Our algorithm is based on the motion adaptive (MA) method which combines the advantages of intra-field and inter-field method. We propose a block type decision mechanism to predict the video content instead of a blind processing with MC method throughout the entire frame. Additionally, in intra-field method, we propose the edge-base adaptive weight average (EAWA) method to achieve a better performance and smooth the edge and stripe. In order to demonstrate our algorithm, we implement the de-interlacing system on the DSP platform with thorough complexity analysis. Compared to MC method, we not only achieve higher video quality in objective and subjective view, but also consume lower computation power. From the profiling on CPU run-time analysis, the proposed algorithm is only one-fifth of MC method. At the DSP demonstration board, the saving ratio is about 54% to 96%.

Emerging video surveillance technologies are based on foreground detection to achieve event detection automatically. Integration foreground detection with a modern multi-camera surveillance system can significantly increase the surveillance efficiency. The foreground detection often leads to high computational load and increases the cost of surveillance system when a mass deployment of end cameras is needed. This paper proposes a DSP-based foreground detection algorithm. Our algorithm incorporates a temporal data correlation predictor (TDCP) which can exhibit the correlation of data and reduce computation based on this correlation. With the DSP-oriented foreground detection, an adaptive frame rate control is developed as a low cost solution for multi-camera surveillance system. The adaptive frame rate control automatically detects the computational load of foreground detection on multiple video sources and adaptively tunes the TDCP to meet the real-time specification. Therefore, no additional hardware cost is required when the number of deployed cameras is increased. Our method has been validated on a demonstration platform. Performance can achieve real-time CIF frame processing for a 16-camera surveillance system by single-DSP chip. Quantitative evaluation demonstrates that our solution provides satisfied detection rate, while significantly reducing the hardware cost.

In this paper a new watermarking technique which is combined with joint photographic experts group (JPEG) encoding system is presented. This method operates in the frequency domain by embedding a pseudo-random sequence of real numbers in a selected set of discrete cosine transform (DCT) coefficients. The embedded sequence is extracted without restoring the original image to fit the trend in the digital still camera (DSC) system. The proposed technique represents a major improvement on methods relying on the comparison between the watermarked and original images. Experimental results show that the proposed watermarking method is robust to several common image processing techniques, including JPEG compression, noise, and blurring. We also implement the whole design by synthesizing with TSMC 1P4M 0.35 µm standard cell. The chip size is 3.0643.064 mm2 for 46374 gate counts. The simulation speed can reach 50 MHz. The power dissipation is 69 mW at 3.3 V 50 MHz.

Audio applications for mobile phone and portable devices are increasingly popular. To attract consumer interest, a multi-standard design on a single device is the trend of current audio decoder development. This paper presents a configurable common filterbank processor (CCFP) for AC-3, MP3 and AAC audio decoder. It is used as an accelerator for general purpose processors to improve performance. All the filterbank transforms are derived to even- or odd-point IFFT flows. In the architecture, a fully pipelined approach is developed which can be configured for different operation modes. This design is synthesized using UMC 0.18 µm library and takes about 26.7 K gates. By the fast algorithm and fully pipelined architecture, the operation cycles are greatly reduced. Therefore, it can be executed at a very low operation frequency with the range of 1.3 to 3.6 MHz. Besides, the power consumption is only 0.9 mW, 3.2 mW and 1 mW for AC-3, MP3 and AAC respectively. We further port our design on an ARM Integrator platform to make a real play system. On average, over 50% ARM performance loading can be saved and used for handling other applications.