This paper describes technological and operational issues of an image-art-on-demand system, which provides visitors with high-definition images of fine art in a virtual gallery. The system is presented as a typical example of multimedia information service systems on IP over ATM network. The high-definition images of fine arts from a database are interactively selected in a virtual gallery which is generated by an advanced computer graphics (CG) workstation. The generated images of the virtual gallery are transmitted by MPEG-2 over TCP/IP on ATM at 30 frames per second. This system was opened from January 1996 to March 1997 as one project of NTT's joint utilization tests of multimedia communications. As far as we know, this system is the first real-time image-art-on-demand system using MPEG-2 on IP over ATM-WAN to be exhibited to the general public.

This paper proposes and performs the primary feasibility evaluation on Flow Attribute Notification Protocol (FANP), which is a protocol between neighbor CSR (Cell Switch Router) nodes for the management of cut-through packet forwarding, in order to apply label switching paradigm. In cut-through packet forwarding with label switching, a router doesn't have to perform conventional IP packet processing for the received packets. FANP indicates the mapping information between a data-link connection and a packet flow to the neighbor node. FANP defines two key procedures, i. e. , one is the VCID Notification Procedure, and the other is the Flow-ID Notification Procedure. The VCID Notification Procedure lets the label switching paradigm over the label swapped data-link, such as ATM link, though the other label switch architecture can not work over the label swapped data-link. The primary evaluation of FANP has been performed using the prototype system and with the actual packet statistics. The result shows that, with a corporate backbone level, the label switch router system with FANP would work well.

A new cell buffer implementation method, called the counter approach, is presented in this paper. A cell buffer handling CLP with the push out scheme can be implemented using this approach. Also, using this approach, an element switch for a MIN with the window scheme can be realized. The experimental element switch LSI has already been fabricated and tested. The LSI proves the applicability of the counter approach to a high-speed ATM switching system.

In this letter, an economical VLSI switch MWS is proposed. MWS is constructed using a large amount of normal speed RAM and provdies sufficient switching capacity without high speed devices or technology.

A current ATM exchanger consists of ATM switch and ATM interface card is implemented with many LSIs. An investigation of an architecture of the ATM interface card is, therefore, important to decides ATM exchanger's functions and its flexibility. In this paper, we propose an architecture of the ATM interface card to contribute to improving the flexibility and reducing the cost for an ATM exchanger. The key feature of the proposed architecture is both physical layer and ATM layer functions at an interface point are executed by a general-purpose microprocessor and FIFOs. A realization of such architecture is discussed, especially, a software configuration of it is proposed because the physical layer functions have to be executed periodically and should not be interrupted. We developed an evaluation breadboard for such periodic software execution and evaluated the proposed ATM interface card architecture. The evaluation results indicate that a 50 MHz R3000 microprocessor and 5 MHz access speed FIFOs can realize the 6.3-Mbps cell relay interface card.