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[Author] Yoshiaki TAKABATAKE(2hit)

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  • Art Gallery Information Service System on IP Over ATM Network

    Miwako DOI  Kenichi MORI  Yasuro SHOBATAKE  Tadahiro OKU  Katsuyuki MURATA  Takeshi SAITO  Yoshiaki TAKABATAKE  

     
    PAPER-System architecture

      Vol:
    E80-B No:10
      Page(s):
    1415-1420

    This paper describes technological and operational issues of an image-art-on-demand system, which provides visitors with high-definition images of fine art in a virtual gallery. The system is presented as a typical example of multimedia information service systems on IP over ATM network. The high-definition images of fine arts from a database are interactively selected in a virtual gallery which is generated by an advanced computer graphics (CG) workstation. The generated images of the virtual gallery are transmitted by MPEG-2 over TCP/IP on ATM at 30 frames per second. This system was opened from January 1996 to March 1997 as one project of NTT's joint utilization tests of multimedia communications. As far as we know, this system is the first real-time image-art-on-demand system using MPEG-2 on IP over ATM-WAN to be exhibited to the general public.

  • A Software-Based ATM Interface Card and Its Evaluation

    Yoshiaki TAKABATAKE  Mikio HASHIMOTO  Taketoshi TSUJITA  Junichi TAKEDA  Yasuro SHOBATAKE  

     
    PAPER-Switching and Communication Processing

      Vol:
    E80-B No:1
      Page(s):
    127-134

    A current ATM exchanger consists of ATM switch and ATM interface card is implemented with many LSIs. An investigation of an architecture of the ATM interface card is, therefore, important to decides ATM exchanger's functions and its flexibility. In this paper, we propose an architecture of the ATM interface card to contribute to improving the flexibility and reducing the cost for an ATM exchanger. The key feature of the proposed architecture is both physical layer and ATM layer functions at an interface point are executed by a general-purpose microprocessor and FIFOs. A realization of such architecture is discussed, especially, a software configuration of it is proposed because the physical layer functions have to be executed periodically and should not be interrupted. We developed an evaluation breadboard for such periodic software execution and evaluated the proposed ATM interface card architecture. The evaluation results indicate that a 50 MHz R3000 microprocessor and 5 MHz access speed FIFOs can realize the 6.3-Mbps cell relay interface card.