IEICE TRANSACTIONS on Communications
A Software-Based ATM Interface Card and Its Evaluation
Summary :
A current ATM exchanger consists of ATM switch and ATM interface card is implemented with many LSIs. An investigation of an architecture of the ATM interface card is, therefore, important to decides ATM exchanger's functions and its flexibility. In this paper, we propose an architecture of the ATM interface card to contribute to improving the flexibility and reducing the cost for an ATM exchanger. The key feature of the proposed architecture is both physical layer and ATM layer functions at an interface point are executed by a general-purpose microprocessor and FIFOs. A realization of such architecture is discussed, especially, a software configuration of it is proposed because the physical layer functions have to be executed periodically and should not be interrupted. We developed an evaluation breadboard for such periodic software execution and evaluated the proposed ATM interface card architecture. The evaluation results indicate that a 50 MHz R3000 microprocessor and 5 MHz access speed FIFOs can realize the 6.3-Mbps cell relay interface card.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E80-B No.1 pp.127-134
- Publication Date
- 1997/01/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- Switching and Communication Processing
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Yoshiaki TAKABATAKE, Mikio HASHIMOTO, Taketoshi TSUJITA, Junichi TAKEDA, Yasuro SHOBATAKE, "A Software-Based ATM Interface Card and Its Evaluation" in IEICE TRANSACTIONS on Communications,
vol. E80-B, no. 1, pp. 127-134, January 1997, doi: .
Abstract: A current ATM exchanger consists of ATM switch and ATM interface card is implemented with many LSIs. An investigation of an architecture of the ATM interface card is, therefore, important to decides ATM exchanger's functions and its flexibility. In this paper, we propose an architecture of the ATM interface card to contribute to improving the flexibility and reducing the cost for an ATM exchanger. The key feature of the proposed architecture is both physical layer and ATM layer functions at an interface point are executed by a general-purpose microprocessor and FIFOs. A realization of such architecture is discussed, especially, a software configuration of it is proposed because the physical layer functions have to be executed periodically and should not be interrupted. We developed an evaluation breadboard for such periodic software execution and evaluated the proposed ATM interface card architecture. The evaluation results indicate that a 50 MHz R3000 microprocessor and 5 MHz access speed FIFOs can realize the 6.3-Mbps cell relay interface card.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e80-b_1_127/_p
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@ARTICLE{e80-b_1_127,
author={Yoshiaki TAKABATAKE, Mikio HASHIMOTO, Taketoshi TSUJITA, Junichi TAKEDA, Yasuro SHOBATAKE, },
journal={IEICE TRANSACTIONS on Communications},
title={A Software-Based ATM Interface Card and Its Evaluation},
year={1997},
volume={E80-B},
number={1},
pages={127-134},
abstract={A current ATM exchanger consists of ATM switch and ATM interface card is implemented with many LSIs. An investigation of an architecture of the ATM interface card is, therefore, important to decides ATM exchanger's functions and its flexibility. In this paper, we propose an architecture of the ATM interface card to contribute to improving the flexibility and reducing the cost for an ATM exchanger. The key feature of the proposed architecture is both physical layer and ATM layer functions at an interface point are executed by a general-purpose microprocessor and FIFOs. A realization of such architecture is discussed, especially, a software configuration of it is proposed because the physical layer functions have to be executed periodically and should not be interrupted. We developed an evaluation breadboard for such periodic software execution and evaluated the proposed ATM interface card architecture. The evaluation results indicate that a 50 MHz R3000 microprocessor and 5 MHz access speed FIFOs can realize the 6.3-Mbps cell relay interface card.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - A Software-Based ATM Interface Card and Its Evaluation
T2 - IEICE TRANSACTIONS on Communications
SP - 127
EP - 134
AU - Yoshiaki TAKABATAKE
AU - Mikio HASHIMOTO
AU - Taketoshi TSUJITA
AU - Junichi TAKEDA
AU - Yasuro SHOBATAKE
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E80-B
IS - 1
JA - IEICE TRANSACTIONS on Communications
Y1 - January 1997
AB - A current ATM exchanger consists of ATM switch and ATM interface card is implemented with many LSIs. An investigation of an architecture of the ATM interface card is, therefore, important to decides ATM exchanger's functions and its flexibility. In this paper, we propose an architecture of the ATM interface card to contribute to improving the flexibility and reducing the cost for an ATM exchanger. The key feature of the proposed architecture is both physical layer and ATM layer functions at an interface point are executed by a general-purpose microprocessor and FIFOs. A realization of such architecture is discussed, especially, a software configuration of it is proposed because the physical layer functions have to be executed periodically and should not be interrupted. We developed an evaluation breadboard for such periodic software execution and evaluated the proposed ATM interface card architecture. The evaluation results indicate that a 50 MHz R3000 microprocessor and 5 MHz access speed FIFOs can realize the 6.3-Mbps cell relay interface card.
ER -
English
