1-2hit |
Yoshihiro OHBA Masayuki MURATA Hideo MIYAHARA
In this paper, we study a dynamic bandwidth control which is expected an effective use of network resources in transmitting highly bursty traffic generated by, e.g., interconnected LAN systems. First, a new LAN traffic model is proposed in which correlation of not only packet interarrival times but also packet lengths are considered. An analytic model for a LAN-ATM gateway is next introduced. It employs the dynamic bandwidth control using the proposed LAN traffic model and some performance measures are derived by it. The analytic model takes into account the probability that a bandwidth increase request may be rejected. Finally, some numerical examples are provided using the analysis method and performance comparisons between the dynamic and fixed bandwidth controls are made. As a result, it is quantitatively indicated that () if the equivalent bandwidth is used in average, the dynamic bandwidth control keeps packet and cell loss rates one to two orders lower than the fixed bandwidth control, () when the more strict QOS in terms of loss rate is requested, the dynamic bandwidth control can become more effective.
Yukio KAMATANI Yoshihiro OHBA Yoshimitsu SHIMOJO Koutarou ISE Masahiko MOTOYAMA Toshitada SAITO
Asynchronous Transfer Mode (ATM) is a promised bearer transmission service for high speed multimedia LAN. Recently, high speed multimedia ATM LAN products have been available. Therefore, in order to interconnect them, the multimedia backbone LAN, which has the expandable high throughput over 10Gbps, supporting multicast, multi-QoS, and many interfaces including 622 Mbps, will be widely required. In this paper, the VLSI oriented input and output buffered switch architecture is proposed as the hardware architecture for multimedia backbone switch node. This paper describes that the chip set consisting of four VLSIs, that is, the switch element, the switch access, the distributor/arbiter, and the multiplexer/demultiplexer, can realize the backbone switch core, and the main specifications required to each VLSI are derived.