A boosted bit line program scheme is proposed for low operating voltage in the multi-level-cell (MLC) NAND flash memory. Our BL to BL boosting scheme, which uses the BL coupling capacitance, is applied to achieve a higher channel potential than is possible with Vcc, so that the Vpass window margin is improved by up to 59% in 40 nm MLC NAND flash memory with 2.7 V Vcc. In the case of 1.8 V Vcc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2.7 V Vcc.

A new low voltage operation of high voltage switching technique, which is capable of reducing leakage current by an order of three compared to conventional circuits, has been developed for sub-1.8 V low voltage mobile NAND flash memory. In addition, by using the proposed high voltage switch, chip size scaling can be realized due to reduced a minimum required space between the N-wells of selected and unselected blocks for isolation. The proposed scheme is essential to achieve low power operation NAND Flash memory, especially for mobile electronics.