Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory
Summary :
A boosted bit line program scheme is proposed for low operating voltage in the multi-level-cell (MLC) NAND flash memory. Our BL to BL boosting scheme, which uses the BL coupling capacitance, is applied to achieve a higher channel potential than is possible with Vcc, so that the Vpass window margin is improved by up to 59% in 40 nm MLC NAND flash memory with 2.7 V Vcc. In the case of 1.8 V Vcc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2.7 V Vcc.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.3 pp.423-425
- Publication Date
- 2010/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.423
- Type of Manuscript
- LETTER
- Category
- Electronic Circuits
Authors
Keyword
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Youngsun SONG, Ki-Tae PARK, Myounggon KANG, Yunheub SONG, Sungsoo LEE, Youngho LIM, Kang-Deog SUH, "Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 3, pp. 423-425, March 2010, doi: 10.1587/transele.E93.C.423.
Abstract: A boosted bit line program scheme is proposed for low operating voltage in the multi-level-cell (MLC) NAND flash memory. Our BL to BL boosting scheme, which uses the BL coupling capacitance, is applied to achieve a higher channel potential than is possible with Vcc, so that the Vpass window margin is improved by up to 59% in 40 nm MLC NAND flash memory with 2.7 V Vcc. In the case of 1.8 V Vcc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2.7 V Vcc.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.423/_p
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@ARTICLE{e93-c_3_423,
author={Youngsun SONG, Ki-Tae PARK, Myounggon KANG, Yunheub SONG, Sungsoo LEE, Youngho LIM, Kang-Deog SUH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory},
year={2010},
volume={E93-C},
number={3},
pages={423-425},
abstract={A boosted bit line program scheme is proposed for low operating voltage in the multi-level-cell (MLC) NAND flash memory. Our BL to BL boosting scheme, which uses the BL coupling capacitance, is applied to achieve a higher channel potential than is possible with Vcc, so that the Vpass window margin is improved by up to 59% in 40 nm MLC NAND flash memory with 2.7 V Vcc. In the case of 1.8 V Vcc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2.7 V Vcc.},
keywords={},
doi={10.1587/transele.E93.C.423},
ISSN={1745-1353},
month={March},}
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TY - JOUR
TI - Boosted Bit Line Program Scheme for Low Operating Voltage MLC NAND Flash Memory
T2 - IEICE TRANSACTIONS on Electronics
SP - 423
EP - 425
AU - Youngsun SONG
AU - Ki-Tae PARK
AU - Myounggon KANG
AU - Yunheub SONG
AU - Sungsoo LEE
AU - Youngho LIM
AU - Kang-Deog SUH
PY - 2010
DO - 10.1587/transele.E93.C.423
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2010
AB - A boosted bit line program scheme is proposed for low operating voltage in the multi-level-cell (MLC) NAND flash memory. Our BL to BL boosting scheme, which uses the BL coupling capacitance, is applied to achieve a higher channel potential than is possible with Vcc, so that the Vpass window margin is improved by up to 59% in 40 nm MLC NAND flash memory with 2.7 V Vcc. In the case of 1.8 V Vcc, the margin of the proposed scheme is 12% higher than one of the conventional schemes at 2.7 V Vcc.
ER -
English
