Multiple patterning lithography allows fine patterns beyond lithography limit, but it suffers from a large process cost. In this paper, we address a method to reduce the number of V0 masks; it consists of two sub-problems. First, stitch-induced via (SIV) is introduced to reduce the number of V0 masks. It involves the redesign of standard cells to replace some vias in V0 layer with SIVs, such that the remaining vias can be assigned to the reduced masks. Since SIV formation requires metal stitches in different masks, SIV replacement and metal mask assignment should be solved simultaneously. This sub-problem is formulated as integer linear programming (ILP). In the second sub-problem, inter-row via conflict aware detailed placement is addressed. Single row placement optimization is performed for each row to remove metal and inter-row via conflicts, while minimizing cell displacements. Since it is time consuming to consider many cell operations at once, we apply a few operations iteratively, where different operations are applied to each iteration and to each cell depending on whether the cell has a conflict in the previous iteration. Remaining conflicts are then removed by mapping conflict cells to white spaces. To this end, we minimize the number of cells to move and maximize the number of large white spaces before mapping. Experimental results demonstrate that the cell placement with two V0 masks is completed by proposed methods, with 7 times speedup and 21% reduction in total cell displacement, compared to conventional detailed placement.

This paper propose a structure of standard cells where the P/N boundary ratio of each cell can be independently customized for near-threshold operation. Lowering the supply voltage is one of the most promising approaches for reducing the power consumption of VLSI circuit, however, this causes an increase of imbalance between rise and fall delays for cells having transistor stacks. Conventional cell library with fixed P/N boundary is not efficient to compensate this delay imbalance. Proposed structure achieves individual P/N boundary ratio optimization for each standard cell, therefore it cancels the imbalance between rise and fall delays at the expense of cell area. Proposed structure is verified using measured result of Ring Oscillator circuits and simulation result of benchmark circuits in 65nm CMOS. The experiments with ISCAS'85 benchmark circuits demonstrate that the standard cell library consisting of the proposed cells reduces the power consumption of the benchmark circuits by 16% on average without increasing the circuit area, compared to that of the same circuit synthesized with a library which is not optimized for the near-threshold operation.

This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35 µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.

For mobile telecommunication systems, it is important to accurately predict the propagation-path loss in terms of the estimation of the radiowave coverage area. The propagation-path loss has been estimated in a median obtained spatially from many received amplitudes (envelopes) within a region of several tens times as long as the wavelength, rather than in the envelopes themselves. Although ray tracing can obtain the envelopes and their median that reflect the site-dependent characteristics, the estimated median sometimes does not agree with the measured one. Therefore, the accuracy improvement has been expected. In this paper, an accuracy improvement is achieved by substituting a median with random phases for the median obtained spatially from many envelopes. The characteristic function method is used to obtain the cumulative distribution function and the median analytically where the phases are randomized. In a multipath environment, the phase-estimation error accompanying the location error of the ray tracing input influences the spatially obtained median. The phase-randomizing operation reduces the effects of the phase-estimation error on the median prediction. According to our estimation, improvements in accuracy of 4. 9 dB for the maximum prediction error and 2. 9 dB for the RMS prediction error were achieved. In addition, a probability-based cell-design method that takes the radiowave arrival probability and the interference probability into consideration is possible by using the percentiles obtained by the characteristic function method and the cell-design examples are shown in this paper.

Non-uniform traffic can affect communications quality in microcell systems, and this disparity in communications quality between base stations (BSs) lowers the system efficiency in CDMA systems. If traffic distribution and propagation conditions are already known during the introduction of a CDMA system, it is desirable to design cell areas according to the non-uniformity of traffic distribution and BS locations. Cell area is determined by the transmission power of the pilot-signal from the BS and it is necessary to control the transmission power of mobile stations in the uplink, which is determined by the desired power level at the BS, according to the cell area. The disparity in communications quality can be rectified by optimally designing the two parameters of the pilot-signal power and desired power level. This paper describes an algorithm for setting both the pilot-signal power and the desired power level during the cell design stage in CDMA systems. The proposed algorithm operates that the communications qualities of all BSs in the system converge to average quality by adjusting the two parameters. The parameters of all BSs in the whole system can be determined through computer calculation. Through performance evaluations, we confirmed that the average SIRs of all BSs attained almost the same value and the variance between the BSs was less than half by adopting the cell design algorithm when there was dispersion in BS placement. This algorithm is also effective using the actual measured SIR after a system has been established.