A low-voltage and low-power RF mixer for WCDMA applications is presented. The paper presents a novel topology mixer that leads to a better performance in terms of isolation and power consumption for low supply voltage. The measuring results of the proposed mixer achieve: 7 dB power conversion gain, 10.4 dB double side band (DSB) noise figure, -2 dBm input third-order intercept point (IIP3), and the total dc power consumption of this mixer including output buffers is 2.2 mW from a 1 V supply voltage. The current output buffer is about 1.96 mW, the excellent LO-RF, LO-IF and RF-IF isolation achieved up to 49 dB, 39.5 dB and 57.3 dB, respectively.

This paper presents a frequency-controllable image rejection mixer in heterodyne architecture for 2 GHz applications based on TSMC 0.18 µm CMOS technology. The designed mixer uses a notch filter to suppress the image signal and allows precise tuning the image frequencies. An image rejection of 20-70 dB is obtained in a 200 MHz of bandwidth. The simulation results show single-side band (SSB) NF is improved 3.7 dB, the voltage conversion gain of 14.7 dB, improved by more than 4 dB. The circuit operates at the supply voltage of 1.8 V, and dissipates 11.34 mW.

In this paper, a CMOS down-conversion double-balanced mixer is presented with the modified low voltage design technique. The frequencies of the radio frequency (RF) signal, local oscillator (LO) and intermediate frequency (IF) are 2.4 GHz, 2.3 GHz and 100 MHz, respectively. Measurement results of the proposed mixer exhibit 6.7 dB of conversion gain, -18 dBm of input 1 dB compression point (P-1 dB), -8 dBm of input-referred third-order intercept point (IIP3), and 14.7 dB single-side band (SSB) noise figure (NF) while applying -8 dBm LO power and consumes 3.3 mA from 1.8 V supply voltage. It can provide 0.7 dB conversion gain when the supply voltage reduces to 1.3 V. This mixer was fabricated in a 0.35 µm 1P4M standard digital CMOS process and the die size is 1.5 1.1 mm2.