New concept of CMOS nonvolatile memory is presented with demonstration of cell implementations. The memory cell, which is a comparator basically, makes use of comparator offset for storage quantity and the FN stress phenomena for cell programming. We also propose the stress-packet operation which is the relevant programming method to finely control the offset of the memory cell. The memory cell is multiple-time programmable while it is implemented in a standard CMOS process. We fabricated the memory cell arrays of the latch comparator and demonstrated that it is rewritten several times. We also investigated the reliability of cell data retention by monitoring programmed offsets for several months.

As the gate area decreases to the order of a square micron, individual trapping events can be detected as fluctuations between discrete levels of the drain current, known as random telegraph signal (RTS) noise. Many circuit application areas such as CMOS Image sensor and flash memory are already suffering from RTS noise. Especially, in case of flash memory, FN stress causes threshold voltage shift problems due to generation of additional oxide traps, which degrades circuit performance. In this paper, we investigated how FN stress effects on RTS noise behavior in MOSFET and monitored it in both the time domain and frequency domain.