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[Keyword] Hi-Vision(5hit)

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  • Adaptive Block-Propagative Background Subtraction Method for UHDTV Foreground Detection

    Axel BEAUGENDRE  Satoshi GOTO  

     
    PAPER-Image

      Vol:
    E98-A No:11
      Page(s):
    2307-2314

    This paper presents an Adapting Block-Propagative Background Subtraction (ABPBGS) designed for Ultra High Definition Television (UHDTV) foreground detection. The main idea is to detect block after block along the objects in order to skip all areas of the image in which there is no moving object. This is particularly interesting for UHDTV when the objects of interest could represent not even 0.1% of the total area. From a seed block which is determined in a previous iteration, the detection will spread along an object as long as it detects a part of that object. A block history map guaranties that each block is processed only once. Moreover, only small blocks are loaded and processed, thus saving computational time and memory usage. The process of each block is independent enough to be easily parallelized. Compared to 9 state-of-the-art works, the ABPBGS achieved the best results with an average global quality score of 0.57 (1 being the maximum) on a dataset of 4K and 8K UHDTV sequences developed for this work. None of the state-of-the-art methods could process 4K videos in reasonable time while the ABPBGS has shown an average speed of 5.18fps. In comparison, 5 of the 9 state-of-the-art methods performed slower on 270p down-scale version of the same videos. The experiments have also shown that for the process an 8K UHDTV video the ABPBGS can divide the memory required by about 24 for a total of 450MB.

  • Highly Parallel and Fully Reused H.264/AVC High Profile Intra Predictor Generation Engine for Super Hi-Vision 4k4k@60 fps

    Yiqing HUANG  Xiaocong JIN  Jin ZHOU  Jia SU  Takeshi IKENAGA  

     
    PAPER

      Vol:
    E94-C No:4
      Page(s):
    428-438

    One high profile intra predictor generation engine is proposed in this paper. Firstly, hardware level algorithm optimization for intra 88 (I8MB) mode is introduced. The original candidate pixels for generating prediction samples of I8MB are replaced with boundary pixels of intra 44 (I4MB) blocks. Based on this adoption, full data reuse between predictors of I4MB and filtered samples of I8MB can be achieved with almost no quality loss. Secondly, one lossless two-44-block based parallel predictor generation flow is proposed. The original predictor generation flow is optimized from 16 stages to 10 stages for I4MB and Intra 1616 (I16MB), which saves 37.5% processing cycles. For I8MB, similar methodology with different processing order of 44 scaled blocks is introduced. Thirdly, fully utilized hardwired engines for I4MB, I16MB and I8MB are proposed in this paper. Except DC (direct current) and plane modes, full data reuse among all intra modes of high profile can be achieved. Fourthly, for DC mode, one combined predictor generation process is introduced and predictor generation of I16MB's DC mode is merged into the process of I4MB's DC mode. Moreover, by configuring proposed hardwired engines, predictor generation of I16MB's plane mode and chrominance plane mode can be accomplished with only 50% cycles of original design. Totally, when compared with original full-mode design and latest dynamic mode reused design, the proposed predictor generation engine can achieve 89.5% and 73.2% saving of processing cycles, respectively. Synthesized by TSMC 0.18 µm technology under worst work conditions (1.62 V, 125°C), with 380 MHz and 37.2 k gates, the proposed design can handle real-time high profile intra predictor generation of Super Hi-Vision 4 k4 k@60 fps. The maximum work frequency of our design under worst condition is 468 MHz.

  • Development of Millimeter-Wave Mobile Camera and Performance Improvement in Outdoor LOS Environment

    Shinichi SUZUKI  Takayuki NAKAGAWA  Tetsuomi IKEDA  

     
    PAPER

      Vol:
    E93-A No:11
      Page(s):
    2099-2107

    The Millimeter-wave Mobile Camera (MiMoCam) developed by NHK STRL uses millimeter-wave band (42 GHz/55 GHz) to transmit Hi-Vision TV picture with high quality and low latency. Multiple-input multiple-output (MIMO) technology which uses a number of antennas at both the transmitter and receiver can be adapted to use to transmit higher quality Hi-Vision TV picture. The camera was intended to be used in a studio environment where there is a high degree of multi-path, however there are also many requests for the MiMoCam to be used outdoor. This will present a different channel statistics where the camera will be operating in a near line-of-sight (LOS) environment without much reflected waves. We have conducted an outdoor transmission test and measured the outdoors transmission performance of the proposed MIMO system to clarify the possibility of using the MiMoCam in outdoor environment. This paper introduces the features of the MiMoCam system and the MIMO transmission technique used in the MiMoCam and presents the findings of this outdoor test. It was also confirmed that channel correlation of the MIMO propagation channels were suppressed by using orthogonally polarized waves and bit error rate (BER) characteristics with respect to the average receiving carrier-to-noise ratio (CNR) was improved. Finally, we could find the feasibility of the MiMoCam outdoor operation from these results.

  • Highly Parallel Fractional Motion Estimation Engine for Super Hi-Vision 4k4k@60 fps

    Yiqing HUANG  Takeshi IKENAGA  

     
    PAPER

      Vol:
    E93-C No:3
      Page(s):
    244-252

    One Super Hi-Vision (SHV) 4k4k@60 fps fractional motion estimation (FME) engine is proposed in our paper. Firstly, two complexity reduction schemes are proposed in the algorithm level. By analyzing the integer motion cost of sub blocks in each inter mode, the mode reduction based mode pre-filtering scheme can achieve 48% clock cycle saving compared with previous algorithm. By further check the motion cost of search points around best integer candidate, the motion cost oriented directional one-pass scheme can provide 50% clock cycle saving and 36% reduction in the number of processing units (PU). Secondly, in the hardware level, two parallel improved schemes namely 16-Pel processing and MB-parallel scheme are given out in our paper, which reduces design effort to only 145 MHz for SHV FME processing. Also, quarter sub-sampling is adopted in our design and 75% hardware cost is reduced for each PU. Thirdly, one unified pixel block loading scheme is proposed. About 28.67% to 86.39% pixels are reused and the related memory access is saved. Furthermore, we also give out one parity pixel organization scheme to solve memory access conflict of MB-parallel scheme. By using TSMC 0.18 µm technology in worst work conditions (1.62 V, 125), our FME engine can achieve real-time processing for SHV 4k4k@60 fps with 412k gates hardware.

  • Current Status of Future Television System Development

    Yuichi NINOMIYA  

     
    INVITED PAPER-Multimedia System LSIs

      Vol:
    E77-C No:12
      Page(s):
    1849-1858

    The current state of development of the television broadcasting system of the future is described with regard to LSI development. It is no need to say that television broadcasting systems are very huge and require a large number of inexpensive LSI's. Hi-Vision broadcasting has already been started in Japan. In the United States, a digital terrestrial broadcasting system (ATV) will be standardized in the near future. On the other hand, the situation in Europe remains unclear but MPEG-2 is now in the stage of system finarizing. We also hear much about "multimedia" but the concept of multimedia broadcasting still requires a lot of time to be translated into reality. Some important current technical topics and related basic technologies are also described in this paper. They include DCT, Hybrid DCT coding, error correcting coding, coded modulation, and improvement of the MUSE system. Finally, the discussion considers the relationship between system development and VLSI technology and the importance of mutual understanding between VLSI engineers and system designers. Some possible requirements for VLSI development are also stated.