This paper presents a novel high-speed low-complexity pipelined degree-computationless modified Euclidean (pDCME) algorithm architecture for high-speed RS decoders. The pDCME algorithm allows elimination of the degree-computation so as to reduce hardware complexity and obtain high-speed processing. A high-speed RS decoder based on the pDCME algorithm has been designed and implemented with 0.13-µm CMOS standard cell technology in a supply voltage of 1.1 V. The proposed RS decoder operates at a clock frequency of 660 MHz and has a throughput of 5.3 Gb/s. The proposed architecture requires approximately 15% fewer gate counts and a simpler control logic than architectures based on the popular modified Euclidean algorithm.

In this paper, we present a scheduler that incorporates round robin service within a VirtualClock discipline. Time-stamp based scheduling algorithms attain a low local delay bound and performance guarantee, but are computationally complex. On the other hand, round robin schemes are simple to implement and have computational complexity of O(1), but they are well known for their output burstiness and short-term unfairness. In order to overcome this problem, we combine round robin with VirtualClock in an algorithm we call VCRR. VCRR possesses better fairness than simple round robin, low jitter and a good scheduling delay bound. At the same time, VCRR preserves the O(1) time complexity of round robin. Simulation experiments show VCRR's efficiency in terms of delay performance, jitter and fairness.

The power line communication (PLC) system should be investigated with respect to the influence on electromagnetic environments. Longitudinal conversion loss (LCL) and input impedance are important parameters for evaluating the influence because they are closely related to the radiated, conducted, and inducted emission. An indoor AC mains system consisting of electrical equipment and an AC mains line was modeled by four-port networks, and the LCL and the input impedance were calculated. The parameters of the four-port networks were determined from theory and measurement. The analytical model was examined using a simple network and the results show that the calculated values agreed with the measured ones. The LCL and the input impedance were investigated at the AC mains port in some existing buildings, and the measured results almost agreed with the calculated results derived from the indoor AC mains system model.