Metadata registry (MDR) is based on the international standard ISO/IEC 11179. The committee of ISO/IEC JTC 1/SC 32, which had standardized the MDR, has started to improvise the MDR, and the improvised version is named extended MDR (XMDR). However, the XMDR does not fully support the ontology concept, and no method is available for mapping ontology registrations onto registries. To overcome the limitations of the outdated XMDR, this paper proposes an extended XMDR (XMDR+) framework. The XMDR+ framework provides a method for mapping of ontology registrations between the metadata registry and ontologies. To improve the functions of the XMDR, we have proposed herein a framework that is capable of defining a model that manages the relations not only among ontological concepts but also among instances, and guarantees the management and storage of their relationships for supporting valid relations of the ontologies.

The increase in the time required for data processing, mask drawing, and inspection of photomask, has led to substantial increase in mask manufacturing cost. This has become one of the major challenges in the semiconductor industry. We have developed a data flow process for mask manufacturing in which we refer to design intent information in order to reduce TAT of mask manufacturing processes. We convert design level information "Design Intent (DI)" into priority information of mask manufacturing data known as "Mask Data Rank (MDR)" so that we can identify and sort out the importance of mask patterns from the view point of the design side. As a result, we can reduce mask writing time and mask inspection time. Our objective is to build efficient data flow conversion system from DI to MDR. In this paper we introduce the idea of MDR and the software system that we built for DI extraction. Then we show the experimental results with actual chip data. Lastly we will discuss related issues and their solutions.

This paper describes a novel Recessed Stacked Capacitor (RSTC) structure for 256 Mbit DRAMs, which can realize the requirements for both fine-pattern delineation with limited depth of focus and high cell capacitance. New technologies involved are the RSTC process, 0.25 µm phase-shift lithography and CVD-tungsten plate technology. An experimental memory array has been fabricated with the above technologies and 25 fF/cell capacitance is obtained for the first time in a 0.61.2 µm2 (0.72 µm2) cell.