One of the technological innovations that has enabled the VLSI semiconductor industry to reduce the transistor size, increase the number of transistors per die, and also follow Moore's law year after year is the fact that an equivalent yield and equivalent testing quality have been ensured for the same die size. This has contributed to reducing the economically optimum production cost (production cost per component) as advocated by Moore. In this paper, we will verify Moore's law using actual values from VLSI manufacturing sites while introducing some of the technical progress that occurred from 1970 to 2010.

Along with the miniaturization of CMOS-LSIs, control methods for LSIs have been extensively developed. The most predominant method is to digitize observed values as early as possible and to use digital control. Thus, many types of analog-to-digital converters (ADCs) have been developed such as temperature, time, delay, and frequency converters. ADCs are the easiest circuits into which digital correction methods can be introduced because their outputs are digital. Various types of calibration method have been developed, which has markedly improved the figure of merits by alleviating margins for device variations. The above calibration and correction methods not only overcome a circuit's weak points but also give us the chance to develop quite new circuit topologies and systems. In this paper, several digital calibration and correction methods for major analog-to-digital converters are described, such as pipelined ADCs, delta-sigma ADCs, and successive approximation ADCs.