An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.

All-CMOS radio transceivers and systems-on-a-chip are rapidly making inroads on a wireless market that for years was dominated by bipolar and BiCMOS solutions. It is not a matter of replacing bipolar transistors in known circuit topologies with FETs; the wave of RF-CMOS brings with it new architectures and unprecedented levels of integration. What are its origins? What is the commercial impact? How will RF-CMOS evolve in the future? This paper offers a retrospective and a perspective.

A fully integrated 2 V 2.4 GHz CMOS low-noise amplifier (LNA) is presented in this paper. A negative resistance circuit is used to reduce the parasitic resistors of the on-chip spiral inductor and increase the quality factor (Q). An inductor is added to the common-source and common-gate transistors of the cascode circuit to improve matching and increase power gain. The LNA is designed according to the tsmc 1P4M 0.35 µm process. The parasitic effect of the on-chip spiral inductor was considered. With a 2 V supply, the power gain of the LNA is 19.5 dB, the noise figure is 2.7 dB, and the power dissipation is 15.2 mW. The input third-order intercept point (IIP3) is 0 dBm. The input -1 dB compression point (P-1dB) is -13.9 dBm. The reverse isolation S12 is -44.1 dB.

A completely symmetric dual-level spiral inductor structure is proposed. The symmetry, area efficiency, the size dependence of the coupling factor, and the quality factors of the dual-level inductors are evaluated and compared with that of the single-level. This work demonstrates that, with most RF applications, the dual-level inductors are the better choice than the single-level.

An RF IC for a 1.1-V VHF paging receiver is developed. In order to reduce the number of components, it employs direct-conversion frequency shift keying (FSK) architecture. The RF IC adopts two new gain control circuits so as to achieve a wide input dynamic range with only a 1.1 V power supply. One is a low-voltage, low-noise, low-distortion RF amplifier and the other is a low-voltage AGC amplifier. By applying these new circuit technologies, the RF IC achieves a voltage gain of 50.5 dB and a noise figure of 4.3 dB with only 2.0 mW power consumption. Overall, the paging receiver achieves a high sensitivity of -130 dBm and low-intermodulation sensitivity of -37 dBm with bit error rate of 310-2. This paper describes the new high-frequency low-voltage circuit technologies applied in the RF IC.