The virtual memory functions in real-time operating systems have been used in embedded systems. Recent RISC processors provide virtual memory supports through software-managed Translation Lookaside Buffer (TLB) in software. In real-time aspects of the embedded systems, managing TLB entries is the most important because overhead at TLB miss time gives a great effect to overall performance of the system. In this paper, we propose several TLB management algorithms in MIPS processors. In the algorithms, a replaced TLB entry is randomly chosen or managed. We analyze the algorithms by comparing overheads at task switching times and TLB miss times.

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.

We Propose an integrated design and test assistance method for pipelined processors. Our approach generates behavioral-level test environments for pipeline control mechanisms from a machine-readable specification. It includes automatic generation of test programs and behavioral descriptions. Verification can be done by applying logic simulation to both the designers' descriptions and the behavioral descriptions, and then comparing the results. We have implemented an experimental system that enumerates all hazard patterns--instruction patterns that cause pipeline hazards--from the specifications, and generates the test programs and the behavioral descriptions for the pipeline controllers. The test programs cover all of the hazard patterns. The behavioral descriptions can manipulate any instruction stream. Experimental results for several RISC processors show that actual hazard patterns are too numerous to be easily enumerated by hand. Using workstations, our system can generate the test programs that cover all of the patterns, taking a few minutes. Results suggest that the system can be used to evaluate pipeline design.