This paper describes the analysis of the Stacked-Surrounding Gate Transistor (S-SGT) DRAM for the high speed and low voltage operation. The S-SGT DRAM is based on the new three dimensional (3D)-building memory array technology. In terms of the bit-lines signal voltage for read operation, it is found that the signal voltage of the S-SGT DRAM is larger than that of the conventional planar DRAM, the NAND-structured DRAM, and the SGT DRAM. The signal voltage of the S-SGT DRAM was found to depend on the pillar radius, the distance between the bit-line and the substrate, and the number of cells connected to one bit-line in comparison with the above three kinds of conventional DRAMs. Especially, with reducing the pillar radius (R), the signal voltage of the S-SGT DRAM becomes larger. In the concrete, in case that R is 0. 25 µm, the signal voltage of the S-SGT DRAM is about 160%, 160% and 120% in comparison with the planar DRAM, the SGT DRAM and the NAND-structured DRAM, respectively. Therefore, the S-SGT DRAM can realize larger S/N ratio. This advantage can realize the high speed and low voltage operation. Moreover, in case that the signal voltage is constant (0.15 V), the maximum number of cells connected to one bit-line for the S-SGT DRAM is about 2 times in comparison with the planar DRAM. This advantage makes it possible to reduce the number of both sense amplifiers and bit-lines. This is very suitable for reducing the total chip size of the S-SGT DRAM. Above all, it was found that the S-SGT DRAM is one of candidates for the high speed and low voltage operation DRAM in the future.