In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.

Logic encryption is an IC protection technique which inserts extra logic and key inputs to hide a circuit's functionality. An encrypted circuit needs to be activated with a secret key for being functional. SAT attack and Removal attack are two most advanced decryption methods that have shown their effectiveness to break most of the existing logic encryption methods within a few hours. In this paper, we propose SMARTLock, a SAT attack and reMoval Attack-Resistant Tree-based logic Locking method, for resisting them simultaneously. To encrypt a circuit, the method finds large AND and OR functions in it and encrypts them by inserting duplicate tree functions. There are two types of structurally identical tree encryptions that aim to resist SAT attack and Removal attack, respectively. The experimental results show that the proposed method is effective for encrypting a set of benchmarks from ISCAS'85, MCNC, and IWLS. 16 out of 40 benchmarks encrypted by the proposed method with the area overhead of no more than 5% are uncrackable by SAT attack within 5 hours. Additionally, compared to the state-of-the-art logic encryption methods, the proposed method provides better security for most benchmarks.