IEICE TRANSACTIONS on Fundamentals
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level
Summary :
In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E107-A No.3 pp.583-591
- Publication Date
- 2024/03/01
- Publicized
- 2023/09/04
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.2023VLP0018
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- VLSI Design Technology and CAD
Authors
Masayoshi YOSHIMURA
Kyoto Sangyo University
Atsuya TSUJIKAWA
Nihon University
Toshinori HOSOKAWA
Nihon University
Keyword
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Masayoshi YOSHIMURA, Atsuya TSUJIKAWA, Toshinori HOSOKAWA, "CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level" in IEICE TRANSACTIONS on Fundamentals,
vol. E107-A, no. 3, pp. 583-591, March 2024, doi: 10.1587/transfun.2023VLP0018.
Abstract: In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.2023VLP0018/_p
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@ARTICLE{e107-a_3_583,
author={Masayoshi YOSHIMURA, Atsuya TSUJIKAWA, Toshinori HOSOKAWA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level},
year={2024},
volume={E107-A},
number={3},
pages={583-591},
abstract={In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.},
keywords={},
doi={10.1587/transfun.2023VLP0018},
ISSN={1745-1337},
month={March},}
Copy
TY - JOUR
TI - CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 583
EP - 591
AU - Masayoshi YOSHIMURA
AU - Atsuya TSUJIKAWA
AU - Toshinori HOSOKAWA
PY - 2024
DO - 10.1587/transfun.2023VLP0018
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E107-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2024
AB - In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design company to design a VLSI. Thus, design companies purchase IP cores from third-party IP vendors and design only the necessary parts. On the other hand, since IP cores have the disadvantage that copyright infringement can be easily performed, logic locking has to be applied to them. Functional logic locking methods using TTLock are resilient to SAT attacks however vulnerable to FALL attacks. Additionally, it is difficult to design logic locking based on TTLock at the gate level. This paper proposes a logic locking method, CRLock, based on SAT attack and FALL attack resistance at the register transfer level. The CRLock is a logic locking method for controllers at RTL in which the designer selects a protected input pattern and modifies the controller based on the protection input pattern. In experimental results, we applied CRLock to MCNC'91 benchmark circuits and showed that all circuits are resistant to SAT and FALL attacks.
ER -
English
