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[Keyword] SFQ circuits(2hit)

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  • 50 GHz Demonstration of an Integer-Type Butterfly Processing Circuit for an FFT Processor Using the 10 kA/cm2 Nb Process

    Yosuke SAKASHITA  Yuki YAMANASHI  Nobuyuki YOSHIKAWA  

     
    PAPER

      Vol:
    E98-C No:3
      Page(s):
    232-237

    We are developing a fast Fourier transform (FFT) processor using high-speed and low-power single-flux-quantum (SFQ) circuits. Our main concern is the development of an SFQ butterfly processing circuit, which is the core processing circuit in the FFT processor. In our previous study, we have confirmed the complete operation of an integer-type butterfly processing circuit using the AIST 2.5 kA/cm$^{2}$ Nb standard process at the frequency of 25 GHz. In this study, we have designed an integer-type butterfly processing circuit using the AIST 10,kA/cm$^{2}$,Nb advanced process and confirmed its high-speed operation at the maximum frequency of 50,GHz.

  • Design and Demonstration of a Single-Flux-Quantum Multi-Stop Time-to-Digital Converter for Time-of-Flight Mass Spectrometry

    Kyosuke SANO  Yuki YAMANASHI  Nobuyuki YOSHIKAWA  

     
    PAPER

      Vol:
    E97-C No:3
      Page(s):
    182-187

    We have been developing a superconducting time-of-flight mass spectrometry (TOF-MS) system, which utilizes a superconductive strip ion detector (SSID) and a single-flux-quantum (SFQ) multi-stop time-to-digital converter (TDC). The SFQ multi-stop TDC can measure the time intervals between multiple input signals and directly convert them into binary data. In this study, we designed and implemented 24-bit SFQ multi-stop TDCs with a 3×24-bit FIFO buffer using the AIST Nb standard process (STP2), whose time resolution and dynamic range are 100ps and 1.6ms, respectively. The timing jitter of the TDC was investigated by comparing two types of TDCs: one uses an on-chip SFQ clock generator (CG) and the other uses a microwave oscillator at room temperature. We confirmed the correct operation of both TDCs and evaluated their timing jitter. The experimentally-obtained timing jitter is about 40ns and 700ps for the TDCs with and without the on-chip SFQ CG, respectively, for the measured time interval of 50µs, which linearly increases with increase of the measured time interval.